Cu capping layer deposition with improved integrated circuit...

Details Cu capping layer deposition with improved integrated circuit... Cu capping layer deposition with improved integrated circuit...

2005-05-24

2005-05-24

Sarkar, Asok Kumar (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S643000, C438S653000, C438S676000, C438S680000, C438S687000

Reexamination Certificate

active

06897144

ABSTRACT:
The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu using dual frequency powers, holding the high frequency power constant and controlling the compressive stress of the deposited silicon nitride capping layer by varying the low frequency power to the susceptor, thereby enabling reduction of the compressive stress below about 2×107Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3diluted with N2, and then depositing the silicon nitride capping layer by plasma enhanced chemical vapor deposition, while varying the low frequency power between about 100 to about 300 watts. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

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Wolf and Tauber, “Silicon processing for the VLSI Era” vol. 1, p. 192, Lattice Press (1986).

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