Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-03-24
2002-08-20
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S698000, C438S125000
Reexamination Certificate
active
06437433
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package having a rail configuration which allows multiple chip packages to be quickly, easily and inexpensively assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages which each include a rail configuration. The inclusion of rail members in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significantly greater simplicity in such assembly.
BRIEF SUMMARY OF THE INVENTION
In accordance with a first embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising an interconnect sub-assembly. The interconnect sub-assembly itself comprises an interconnect substrate which defines opposed, generally planar top and bottom surfaces. The interconnect substrate preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The interconnect substrate is preferably flexible, though the same may alternatively be of rigid construction. If flexible, the interconnect substrate is preferably fabricated from a polyamide. If of rigid construction, the interconnect substrate is preferably fabricated from a ceramic material.
Disposed on the interconnect substrate are first, second and third conductive pad arrays, with the second and third pad arrays extending along respective ones of the lateral peripheral edge segments of the interconnect substrate and being disposed on opposite sides of the first conductive pad array. Additionally, the second and third conductive pad arrays are each electrically connected to the first conductive pad array. The electrical connection of the second and third conductive pad arrays to the first conductive pad array is preferably facilitated by conductive tracings which are formed in accordance with conventional etching techniques.
In the chip package of the first embodiment, the first conductive pad array comprises a first set of pads disposed on the top surface of the interconnect substrate, with the second conductive pad array comprising second and third sets of pads disposed on respective ones of the top and bottom surfaces and arranged in identical patterns such that the pads of the second set are aligned with respective ones of the pads of the third set. Similar to the second conductive pad array, the third conductive pad array comprises fourth and fifth sets of pads disposed on respective ones of the top and bottom surfaces and arranged in identical patterns such that the pads of the fourth set are aligned with respective ones of the pads of the fifth set. The pads of the second set are electrically connected to respective ones of the pads of the third set, with the pads of the fourth set being electrically connected to respective ones of the pads of the fifth set. Such electrical connection may be facilitated through the use of vias extending through the interconnect substrate or conductive tracings which extend about the lateral peripheral edge segments thereof.
The interconnect sub-assembly of the chip package of the first embodiment further comprises first and second identically configured rail members which are each attached to the interconnect substrate. The first and second rail members each have a generally rectangular configuration and define opposed, generally planar top and bottom surfaces. Disposed on the first rail member is a fourth conductive pad array, while disposed on the second rail member is a fifth conductive pad array. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays.
The fourth conductive pad array itself preferably comprises sixth and seventh sets of pads which are disposed on respective ones of the top and bottom surfaces of the first rail member and arranged in identical patterns such that the pads of the sixth set are aligned with respective ones of the pads of the seventh set. Similarly, the fifth conductive pad array preferably comprises eighth and ninth sets of pads which are disposed on respective ones of the top and bottom surfaces of the second rail member and arranged in identical patterns such that the pads of the eighth set are aligned with respective ones of the pads of the ninth set. The pads of the sixth set are electrically connected to respective ones of the pads of the seventh set, with the pads of the eighth set being electrically connected to respective ones of the pads of the ninth set. In the chip package of the first embodiment, the pads of the second through fifth sets (which are disposed upon the interconnect substrate), the pads of the sixth and seventh sets (which are disposed upon the first rail member) and the pads of the eighth and ninth sets (which are disposed upon the second rail member) are arranged in identical patterns.
The interconnect sub-assembly of the chip package of the first embodiment is preferably assembled by attaching the first and second rail members to the interconnect substrate such that either the sixth or seventh sets of pads of the first rail member are electrically connected to respective ones of those pads of the second conductive pad array which are disposed on the bottom surface of the interconnect substrate, and either the eight or ninth sets of pads of the second
Clark Sheila V.
Stetina Brunda Garred & Brucker
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