Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-26
1999-03-09
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438240, 438396, H01L 218242
Patent
active
058799850
ABSTRACT:
A structure and process for fabricating a crown capacitor using a tapered etch and chemical mechanical polishing to form a bottom electrode having an increased area and crown is provided. The tapered etch is used to form a trough in an interlevel dielectric, e.g. SiO.sub.2, and is performed over contact hole forming a crown-like structure. The trough and, optionally, the crown are then covered by a conductor, which is patterned by chemical mechanical polishing.
REFERENCES:
patent: 5235199 (1993-08-01), Hamamoto et al.
patent: 5354716 (1994-10-01), Pors et al.
patent: 5432116 (1995-07-01), Keum et al.
patent: 5451539 (1995-09-01), Ryou
patent: 5550076 (1996-08-01), Chen
patent: 5552334 (1996-09-01), Tseng
patent: 5561311 (1996-10-01), Hamamoto et al.
patent: 5759888 (1998-06-01), Wang et al.
Toru Kaga, et al. .Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's., IEEE Transactions on Electron Devices, vol. 38, No. 2, Feb. 1991, pp. 255-260.
Gambino Jeffrey P.
Kotecki David E.
Anderson Jay H.
Chang Joni
International Business Machines - Corporation
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