Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-08-19
2001-09-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S161000
Reexamination Certificate
active
06291276
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor devices fabricated as integrated circuits and, more particularly, to a structure for cross coupled thin film transistors and a static random access memory (SRAM) cell.
BACKGROUND OF THE INVENTION
Static random access memories (SRAMs) are sometimes used in preference to dynamic random access memories (DRAMs) because SRAMs have faster access times, they require no refresh circuitry and they can be made to have very low power consumption. However, conventional SRAMs are more expensive than DRAMs because an SRAM uses a large number of transistors compared to a DRAM. Hence, DRAMs are preferred in applications where the cost per bit of memory is important.
There are two types of SRAM memory cells in general use today—a six transistor (6T) cell and a four transistor (4T) cell. A typical 6T cell, illustrated in
FIG. 1
, consists of a latch made up of two cross coupled CMOS inverters, which form a circuit known as a flip-flop. In this cell, the load devices Q
3
and Q
4
are p-channel transistors. The pull down transistors, Q
5
and Q
6
, and the access transistors, Q
1
and Q
2
, are n-channel transistors. (The term “pull down” derives from the fact that the output nodes of these transistors are pulled down to substantially ground potential when the transistors are biased to conduction.) The first access transistor Q
1
, the gate of which is controlled by word line WL, provides selective coupling of the true bit line D to storage node A. A second access transistor Q
2
, the gate of which is also controlled by word line WL, provides selective coupling of the complement bit line D′ to storage node B. Since very little power is required to maintain a latched state, 6T SRAMs are often used for memory in battery applications. 6T SRAMs are the most costly SRAMs to manufacture because the 6T cell uses the greatest amount of chip real estate.
A typical 4T SRAM cell, illustrated in
FIG. 2
, is similar to the 6T cell of
FIG. 1
except that the two p-channel load transistors are replaced by resistive elements, R
3
and R
4
. A 4T SRAM is usually less costly to produce than a 6T SRAM because more memory cells can be packed onto each chip. 4T SRAMs are, however, disadvantageous in very low power applications because the resistors consume more current than the p-channel transistors they replace.
In order to overcome the above problems associated with conventional SRAMs, a three transistor (3T) SRAM memory cell was developed. This new SRAM memory cell is described and claimed in my commonly owned and copending application Ser. No. 08/388,873, entitled “Three Transistor Static Random Access Memory Cell”, filed Feb. 14, 1995, incorporated herein by reference. The preferred embodiment of the 3T SRAM described in detail in this copending application combines a DRAM memory cell with a half latch. That SRAM memory cell circuitry includes an access transistor coupled to a capacitor, an n-channel pull down transistor and a p-channel thin film transistor (TFT) which acts as the capacitor pull up device. The gate of the TFT is formed in the same layer of polysilicon in which the capacitor storage node is formed. The source, drain and channel of the p-channel TFT is formed in a separate layer of polysilicon. The gate of the TFT is coupled to the supply voltage V
cc
through back to back diodes, which function as a resistor, and to ground or a substrate voltage through the pull down transistor.
The present invention is directed to a set of cross coupled thin film transistors that are formed on top of one another in vertically adjacent layers of polysilicon. This structural configuration saves valuable chip real estate and, correspondingly, allows for reduced manufacturing costs When used in the memory cell described in my copending application, the first TFT functions as the capacitor pull up device and the second TFT functions as an active load device in place of The back to back diodes described as part of the preferred embodiment in my copending application. Using a TFT instead of back to back diodes as the load device increases the speed of read and write operations in the SRAM. The invented TFT cross coupling structure allows this increase in speed without adding to cell size.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the invention to provide a new compact structural configuration for a pair of cross coupled TFTs.
It is another object to incorporate this structure into an SRAM memory cell to increase the speed of cell operations without adding to cell size.
It is another object to provide a compact 4T SRAM memory cell circuit, layout and structure.
These and other objects and advantages are achieved by a pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. In one preferred version of the invention, the first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer.
In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V
cc
through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V
cc
through the first TFT. In one preferred version of the SRAM memory cell, the first TFT gate is formed in a first polysilicon layer and the first TFT source, drain and channel are formed in a second polysilicon layer, the second polysilicon layer being disposed over and adjacent to the first polysilicon layer. The second TFT gate is formed in the second polysilicon layer and the second TFT source, drain and channel are formed in the first polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. Preferably, the first TFT gate overlaps the second TFT source and the second TFT gate overlaps the first TFT source.
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patent: 5286663 (1994-02-01), Manning
patent: 5388067 (1995-02-01), Sato et al.
patent: 5422499 (1995-06-01), Manning
patent: 5440508 (1995-08-01), Pathak et al.
patent: 5471071 (1995-11-01), Yoshihara
patent: 5625200 (1997-04-01), Lee et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5675185 (1997-10-01), Chen et al.
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Micro)n Technology, Inc.
Niebling John F.
Ormiston & McKinney PLLC
Simkovic Viktor
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