Crackstop structures and methods of making same

Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure

Reexamination Certificate

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Details

C257S618000, C257S620000, C257SE21523, C257SE21532, C438S113000, C438S460000, C438S461000

Reexamination Certificate

active

07955952

ABSTRACT:
An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate.

REFERENCES:
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patent: 6022791 (2000-02-01), Cook et al.
patent: 6271578 (2001-08-01), Mitwalsky et al.
patent: 2007/0102792 (2007-05-01), Wu
patent: 2007/0194409 (2007-08-01), Wang et al.
patent: 2007/0205481 (2007-09-01), Ishida
patent: 2007/0264035 (2007-11-01), Fushimi et al.
patent: 2008/0157285 (2008-07-01), Tokitoh

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