Crack inhibited composite dielectric layer

Details Crack inhibited composite dielectric layer Crack inhibited composite dielectric layer

2002-11-22

2004-12-07

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S778000

Reexamination Certificate

active

06828255

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic products. More particularly, the present invention relates to methods for forming dielectric layers within microelectronic products.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned conductor layers which are separated by dielectric layers.
As microelectronic product integration levels have increased and patterned conductor layer dimensions have decreased, it has become increasingly difficult to form within microelectronic products dielectric layers formed with inhibited cracking. Cracking within dielectric layers is often attributable to physical stress within dielectric layers. In turn, physical stress is often amplified as microelectronic structure dimensions decrease.
It is thus desirable in the art of microelectronic fabrication to fabricate microelectronic products with inhibited dielectric layer cracking. It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the microelectronic fabrication art for forming microelectronic products with desirable properties.
Included but not limiting among the methods are methods disclosed within: (1) Ravi et al., in U.S. Pat. No. 5,976,993 (a laminated layer method for reducing intrinsic stress within a high density plasma chemical vapor deposition (HDP-CVD) deposited dielectric layer); and (2) Jang et al., in U.S. Pat. No. 6,372,664 (an additional laminated layer method for inhibiting cracking within a dielectric layer formed in part employing an HDP-CVD method).
Desirable in the microelectronic fabrication art are additional methods for forming dielectric layers with inhibited cracking.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the invention is to provide a method for forming a dielectric layer within a microelectronic product.
A second object of the invention is to provide a method in accord with the first object, wherein the dielectric layer is formed with inhibited cracking.
In accord with the objects of the invention, the present invention provides a method for forming a microelectronic product.
To practice the method of the invention, there is first provided a substrate having formed thereover a tensile stressed topographic feature. There is then formed over the substrate including the tensile stressed topographic feature a first dielectric layer formed of a fluorosilicate glass (FSG) dielectric material formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. There is then formed over the first dielectric layer a second dielectric layer formed of an undoped silicate glass (USG) dielectric material formed employing an HPD-CVD source radio frequency power only method employing a radio frequency source power of from about 1000 to about 5000 watts absent a bias power.
The present invention provides a method for forming a dielectric layer within a microelectronic product, wherein the dielectric layer is formed with attenuated cracking.
The present invention realizes the foregoing object within the context of an FSG/USG laminate by employing a specific radio frequency source power (and absent a bias power) within an HDP-CVD source radio frequency power only method employed in part for forming the FSG/USG laminate.


REFERENCES:
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patent: 6165915 (2000-12-01), Jang
patent: 6372664 (2002-04-01), Jang et al.
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patent: 2001017242 (2001-03-01), None
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