CPLD for multi-wire keyboard decode with timed power control...

Details CPLD for multi-wire keyboard decode with timed power control... CPLD for multi-wire keyboard decode with timed power control...

2006-12-05

2009-02-03

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S112000, C326S119000

Reexamination Certificate

active

07486106

ABSTRACT:
The present invention is directed to a circuit and a method that features selectively isolating a logic device from a source of power implementing a counter circuit to transmit a signal to a voltage control device to isolate a source of power from a logic device, coupled to a plurality of switching elements, with the voltage control device being coupled to allocate power to the logic device in response to activation of one of said plurality of switching elements. The logic device is typically a programmable logic device. In one embodiment, the voltage control device is a field effect transistor. In another embodiment the voltage control device is a voltage regulator.

REFERENCES:
patent: 7129745 (2006-10-01), Lewis et al.
patent: 7222244 (2007-05-01), Kawahara et al.
patent: 7245148 (2007-07-01), Awalt et al.

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