Corrugated post capacitor and method of fabricating using select

Details Corrugated post capacitor and method of fabricating using select Corrugated post capacitor and method of fabricating using select

1997-05-29

1999-05-25

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438255, 438256, H01L 218242

Patent

active

059077743

ABSTRACT:
A dynamic random access memory cell (20) with increased capacitance and a method of fabricating the cell, including forming a corrugated post capacitor (21) is provided. The method includes depositing a first film (80) having a first etched selectivity and depositing on the first film a second film (82) having a second etched selectivity. These steps of depositing a first film and a second film are repeated at least once to form a plurality of first film layers (80) alternated with a plurality of second film layers (82). A void (58) is etched in the plurality of first and second film layers. The plurality of first and second layers are selectively etched to form a plurality of undercut areas. Silicon is then selectively deposited in the void, and by overgrowing the selectively deposited silicon a portion of the undercut areas is filled with silicon to form a corrugated post storage electrode. The pluralities of first (80) and second (82) film layers are then removed. A layer of rugged polysilicon may be applied to further enhance the surface area of the storage electrode. A capacitor dielectric (48) is then formed over the selectively deposited silicon and a conductive material (50) is formed over the dielectric.

REFERENCES:
patent: 5080933 (1992-01-01), Grupen-Shemansky et al.
patent: 5240871 (1993-08-01), Doan et al.
patent: 5384276 (1995-01-01), Ogawa et al.
patent: 5716884 (1998-02-01), Hsue et al.

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