Corner rounding process for partial vertical transistor

Details Corner rounding process for partial vertical transistor Corner rounding process for partial vertical transistor

2005-08-16

2005-08-16

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S243000, C438S245000, C438S248000

Reexamination Certificate

active

06929996

ABSTRACT:
A double corner rounding process for a partial vertical cell. A first corner rounding process is performed after etching the substrate to form a shallow trench for device isolation. A second corner rounding process is performed after forming shallow trench isolations (STIs) and exposing the corner of the substrate at the active areas in the memory cell array region.

REFERENCES:
patent: 6518146 (2003-02-01), Singh et al.
patent: 2004/0238869 (2004-12-01), Chang et al.
patent: 2005/0012131 (2005-01-01), Chen et al.

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