Core cell structure and corresponding process for NAND-type high

Details Core cell structure and corresponding process for NAND-type high Core cell structure and corresponding process for NAND-type high

1997-12-18

2000-02-08

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257261, 257326, 438266, H01L 29788

Patent

active

060230851

ABSTRACT:
A method of forming a NAND-type flash memory device (200) includes forming a stacked gate flash memory structure (346) for one or more flash memory cells in a core region (305) and forming a transistor structure having a first gate oxide (336) and a gate conductor (338) for both a select gate transistor (344) in the core region (305) and a low voltage transistor (342) in a periphery region (328). In addition, a NAND-type flash memory device (200) includes a core region (305) comprising a stacked gate flash memory cell structure (346) and a select gate transistor (344) and a periphery region (328, 332) comprising a low voltage transistor (342) and a high voltage transistor (350), wherein a structure of the select gate transistor (344) and the low voltage transistor (342) are substantially the same.

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"A 4-Mb NAND EEPROM with Tight Programmed V.sub.t Distribution", Masaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchhi and Fujio Masuoka, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991.

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