Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-18
2002-04-16
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06372577
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to integrated circuits and, in particular, to a flash memory structure and a method of flash memory fabrication wherein a new core cell structure eliminates a stacked gate structure for the select gate transistors while eliminating a core dual oxide manufacturing step. The elimination of the core dual oxide step substantially simplifies the process, eliminates associated tunnel oxide reliability concerns and shrinks the size of the select gate transistor by eliminating the need for a poly1 contact.
BACKGROUND OF THE INVENTION
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1
a
, a memory device such as a flash memory
10
comprises one or more high density core regions
11
and a low density peripheral portion
12
on a single substrate
13
. The high density core regions
11
typically consist of at least one M×N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion
12
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
11
are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art
FIG. 1
b
. Each memory cell
14
has a drain
14
a
, a source
14
b
and a stacked gate
14
c
. A plurality of memory cells
14
connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art
FIG. 1
b
. Each stacked gate
14
c
is coupled to a word line (WL
0
, W
1
, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL
0
, BL
1
, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell
14
can be addressed for programming, reading or erasing functions.
Prior art
FIG. 1
c
represents a fragmentary cross section diagram of a typical memory cell
14
in the core region
11
of prior art
FIGS. 1
a
and
1
b
. Such a cell
14
typically includes the source
14
b
, the drain
14
a
and a channel
15
in a substrate or P-well
16
; and the stacked gate structure
14
c
overlying the channel
15
. The stacked gate
14
c
further includes a thin gate dielectric layer
17
a
(commonly referred to as the tunnel oxide) formed on the surface of the P-well
16
. The stacked gate
14
c
also includes a polysilicon floating gate
17
b
which overlies the tunnel oxide
17
a
and an interpoly dielectric layer
17
c
overlies the floating gate
17
b
. The interpoly dielectric layer
17
c
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer Lastly, a polysilicon control gate
17
d
overlies the interpoly dielectric layer
17
c
. The control gates
17
d
of the respective cells
14
that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art
FIG. 1
b
). In addition, as highlighted above, the drain regions
14
a
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
15
of the cell
14
conducts current between the source
14
b
and the drain
14
a
in accordance with an electric field developed in the channel
15
by the stacked gate structure
14
c.
According to conventional operation, the flash memory cell
14
operates in the following manner. The cell
14
is programmed by applying a relatively high voltage V
G
(e.g., approximately 18 volts) to the control gate
17
d
and connecting the drain, source and P-well to ground. A resulting high electric field across the tunnel oxide
17
a
leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate
17
b
and become trapped in the floating gate
17
b
since the floating gate
17
b
is surrounded by insulators (the interpoly dielectric
17
c
and the tunnel oxide
17
a
). As a result of the trapped electrons, the threshold voltage of the cell
14
increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell
14
created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell
14
, a predetermined voltage V
G
that is greater than the threshold voltage of an erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate
17
d
with a voltage applied between the source
14
b
and the drain
14
a
. If the cell
14
conducts, then the cell
14
has not been programmed (the cell
14
is therefore at a first logic state, e.g., a zero “0”). Likewise, if the cell
14
does not conduct, then the cell
14
has been programmed (the cell
14
is therefore at a second logic state, e.g., a one “1”). Consequently, one can read each cell
14
to determine whether it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell
14
, a relatively high voltage V
S
(e.g., approximately 20 volts) is applied to the P-well
16
and the control gate
17
d
is held at a ground potential (V
G
=0), while the drain
14
a
and the source
14
b
are allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide
17
a
between the floating gate
17
b
and the P-well
16
. The electrons that are trapped in the floating gate
17
b
flow toward and cluster at the portion of the floating gate
17
b
overlying the source region
14
b
and are extracted from the floating gate
17
b
and into the source region
14
b
by way of Fowler-Nordheim tunneling through the tunnel oxide
17
a
. Consequently, as the electrons are removed from the floating gate
17
b
, the cell
14
is erased.
There is a strong need in the art for a flash memory device structure and process for manufacture that improves the performance and reliability of the device while simplifying its method of manufacture.
SUMMARY OF THE INVENTION
The present invention relates to flash memory device structure and a method for its manufacture. In a core portion of a NAND-type flash memory cell, a select gate transistor structure has a structure like that of the periphery low voltage transistor and is fabricated using essentially the same steps as those used in fabricating the periphery low voltage transistor. The select gate transistor structure allows the device to be easily fabricated by eliminating the dual core oxide formation process. Elimination of the dual core oxide process steps reduces the number of process steps and prevents a source of potential contamination prior to the formation of the core tunnel oxide, thereby improving the reliability of the device.
According to another aspect of the present invention, the formation of a select gate transistor structure like that of the periphery low voltage transistor eliminates the stacked gate structure for the select gate transistors and the need for a poly
1
contact to short out the poly
1
and poly
2
layers, thereby advantageously reducing the die area. In addition, eliminating the stacked gate structure for the select gate transistor allows for a channel stop implant to be performed in the select gate transistor region, thereby improving the bit line isolation and decreasing the potential for bit line to bit line punch through.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinaft
Booth Richard
Eschweiler & Associates LLC
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