Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating predominantly semiconductor substrate
Reexamination Certificate
1999-10-07
2002-05-28
Wong, Edna (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating predominantly semiconductor substrate
C205S186000, C205S187000
Reexamination Certificate
active
06395164
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor integrated circuit (IC) manufacturing, and more particularly to, copper metallization deposition techniques in dual damascene IC structures.
Copper wiring in the complemetary metal oxide semiconductor (CMOS) backend-of-line (BEOL) has the following advantages over Al(Cu) wiring: significantly lower resistance, higher allowed current density, and increased scalability. Because for copper is very difficult to etch in a process analogous to that used for aluminum metallization, dual damascene structures are typically patterned in the dielectric and then filled with copper metallization. The industry process of choice for copper filling is electroplating. This is so because of cost and for other technological reasons such as improved electromigration and gap fill.
The prerequisite for electroplating features without voids and defects is the existence of a continuous copper (Cu) strike layer. However, as BEOL dual damascene aspect ratios increase, the task of producing a continuous Cu strike layer for Cu electroplating becomes more challenging. Current state-of-the-art Cu physical vapor deposition (PVD) seed layer deposition techniques are directional by definition, and hence coat horizontal surfaces (field area, trench and via bottoms) more effectively than vertical surfaces (via and trench sidewalls). This inherent limitation may result in discontinuous sidewall coverage as dual damascene dimensions approach sub 0.25 micron dimensions with aspect ratios >3:1, and hence incomplete electroplated fill. What is needed, therefore, is a method for repairing incomplete fill areas to create a continuous Cu strike layer.
SUMMARY OF THE INVENTION
In view of the above, the invention provides a simple, cost-effective conformal Cu electroless touch-up process that repairs any type of continuous or non-continuous Cu seed layer, such as deposited by PVD, collimated PVD, ionized PVD, evaporation, etc., and transforms it into a suitable strike layer for Cu electroplating.
According to the method of the invention, plating copper on a substrate is accomplished by depositing a seed layer on the substrate. The substrate is then coated with a solution including a reducing agent to cause a conformal layer of metal to deposit on a portion of the substrate not covered by the seed layer, thereby repairing discontinuities in the seed layer deposited in the depositing step. The coating step is performed by an electroless process. Afterward, an electroplating process can be performed on the substrate using the seed layer.
The electroless Cu touch-up process thus transforms a non-continuous Cu seed layer into a suitable strike layer through a simple, quick, and cost-efficient manner. The resultant strike layer will then permit the use of higher BEOL dual damascene aspect ratios that will increase chip performance. Another advantage of this process is that existing PVD tool sets can be used and need not be replaced.
These and other features and advantages of the invention will become apparent upon a review of the following detailed description of the presently preferred embodiments of the invention, when viewed in conjunction with the appended drawings.
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Andricacos Panayotis
Fluegel James E.
Gaudiello John G.
Goldblatt Ronald D.
Malhotra Sandra G.
Anderson Jay H.
Wong Edna
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