Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-06
2004-03-16
Le, Dung (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S619000, C438S692000, C438S687000, C438S672000
Reexamination Certificate
active
06706625
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating a barrier cap layer for lines and vias.
BACKGROUND OF THE INVENTION
The current practice uses a copper (Cu)-chemical mechanical polishing (CMP) to planarize the copper surface after filling the line/via by copper electrochemical plating. The Cu-CMP stops on the oxide. A post-CMP silicon nitride (SiN) overlying cap layer is a common integration approach as a barrier layer for the next damascene structure.
U.S. Pat. No. 6,114,243 to Gupta et al. describes: 1) formation of a copper interconnect; 2) a copper-CMP; 3) etch-back of the copper interconnect; and 4) formation of a conductive barrier layer.
U.S. Pat. No. 6,291,332 B1 to Yu et al. describes a reverse plating technique.
U.S. Pat. No. 6,093,647 to Yu et al. describes another reverse plating technique.
U.S. Pat. No. 6,297,158 B1 to Liu et al. describes a copper dual damascene process using electrochemical plating.
U.S. Pat. No. 6,274,499 B1 to Gupta et al. describes a dielectric cap layer over a copper interconnect.
U.S. Pat. No. 5,744,376 to Chan et al. describes a copper interconnect with a top barrier layer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an method of fabricating barrier cap layers over lines and vias.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having an opening formed therein is provided. The substrate having an upper surface. A planarized metal structure is formed within the opening. The planarized metal structure being substantially planar with the upper surface of the substrate. A portion of the planarized metal structure is removed using a reverse-electrochemical plating process to recess the metal structure from the upper surface of the substrate. A barrier cap layer is formed over the substrate and the recessed metal structure. The excess of the barrier cap layer is removed from over the substrate by a planarization process to form the planarized barrier cap layer over the metal structure.
REFERENCES:
patent: 5744376 (1998-04-01), Chan et al.
patent: 6093647 (2000-07-01), Yu et al.
patent: 6114243 (2000-09-01), Gupta et al.
patent: 6274499 (2001-08-01), Gupta et al.
patent: 6291332 (2001-09-01), Yu et al.
patent: 6297158 (2001-10-01), Liu et al.
patent: 6383917 (2002-05-01), Cox
patent: 6537912 (2003-03-01), Agarwal
patent: 6537913 (2003-03-01), Modak
Hsia Liang Ch O
Ping Liu Wu
Sudijono John
Chartered Semiconductor Manufacturing Ltd.
Le Dung
Pike Rosemary L. S.
Saile George O.
Stanton Stephen G.
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