Copper process compatible CMOS metal-insulator-metal...

Details Copper process compatible CMOS metal-insulator-metal... Copper process compatible CMOS metal-insulator-metal...

2000-07-24

2001-12-11

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C438S253000, C257S301000, C257S306000, C257S528000

Reexamination Certificate

active

06329234

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention describes both a structure and method of fabricating copper metal-insulator-metal (MIM) capacitors and thick metal inductors simultaneously, with only one addition mask, for high frequency mixed-signal or Rf, CMOS applications, in a dual damascene trench and via process.
(2) Description of Related Art
As a background to the current invention, in many mixed signal or high frequency Rf applications both high performance, high speed capacitors and inductors are required. Low series resistance, low loss, high Q and low (RC) time constants are required in these high frequency applications for high performance. In addition, it is important to fabricate device structures by processes compatible with CMOS processing with AlCu alloys to pure copper in dual damascene structures.
A metal-insulator-metal (MIM) capacitor is used commonly in high performance applications in CMOS technology. Typically, the capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating layer. Both two parallel plates are conventionally made from Al or AlCu alloys. These metals are patterned and etched needing several photolithography photo masking steps. The thin insulating dielectric layer is usually made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD).
The damascene processing is a “standard” method for fabricating planar copper interconnects. Damascene wiring interconnects (and/or studs) are formed by depositing a dielectric layer on a planar surface, patterning it using photolithography and oxide reactive ion etch (RIE), then filling the recesses with conductive metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with metal. For example, damascene wiring lines can be used to form bit lines in DRAM devices, with processing similar to the formation of W studs in the logic and DRAM devices. In both examples, sputtered Ti/TiN liners, underlying diffusion barriers, have been coated with chemical vapor deposited (CVD) W metal, then polished back to oxide.
In the dual-damascene process, a monolithic stud/wire structure is formed from the repeated patterning of a single thick oxide film followed by metal filling and CMP. First, a relatively thick oxide layer is deposited on a planar surface. The oxide thickness is slightly larger than the desired final thickness of the stud and wire, since a small amount of oxide is removed during CMP. Stud recesses are formed in the oxide using photolithography and RIE that either partially etches through the oxide or traverses the oxide and stops on the underlying metal to be contacted. The wire recesses can then be formed using a separate photolithography step and a timed oxide etching step. If the former stud RIE option is used, the wire etching completes the drilling of the stud holes.
Next, the stud/wire metallization is deposited, then planarized using CMP. The resulting interconnects are produced with fewer process steps than with conventional processing and with the dual damascene process, two layer of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Another metal deposition, besides sputtering techniques, has been adapted as a standard for copper metallization. This technique is electrochemical deposition (ECD) of copper. The electrochemical copper deposition (ECD) still needs, e.g., sputtering techniques, physical vapor deposition (PVD), to deposit thin underlying diffusion barrier film (Ta,TaN) and a conductive “seed” layer of copper.
Related patents and relevant literature now follow as Prior Art, summarized below.
U.S. Pat. No. 5,879,985 entitled “Crown Capacitor Using a Tapered Etch of a Damascene Lower Electrode” granted Mar. 9. 1999 to Gambino et al. shows a capacitor using a damascene process for the lower electrode. Upper capacitor structure has a “crown” type structure.
U.S. Pat. No. 5,406,447 entitled “Capacitor Used in an Integrated Circuit and Comprising Opposing Electrodes Having Barrier Metal Films in Contact with a Dielectric Film” granted Apr. 11, 1995 to Miyazaki teaches a process for a planar metal-insulator-metal (MIM) capacitor. Barrier metal films are composed of platinum, palladium, tantalum, or titanium nitride. The capacitor dielectric material is either tantalum oxide or a perovskite oxide, such as strontium titanate or a composite of lead zirconate and lead titanate, which are ferroelectric type materials.
U.S. Pat. No. 5,208,726 entitled “Metal-Insulator-Metal (MIM) Capacitor-Around-Via Structure for a Monolithic Microwave Integrated Circuit (MMIC) and Method of Manufacturing Same” granted May 4, 1993 to Apel teaches a MIM capacitor structure and method for monolithic microwave IC applications. A low inductance connection is provided between a front side MIM capacitor and a backside ground plane.
U.S. Pat. No. 5,194,932 entitled “Semiconductor Integrated Circuit Device” granted Mar. 16, 1993 to Kurisu teaches a metal-insulator-metal (MIM) capacitor method. The ground pattern, the insulating inter layer, and the power source pattern come together to form a MIM type capacitor.
U.S. Pat. No. 5,293,510 entitled “Semiconductor Device with Ferroelectric and Method of Manufacturing the Same” granted Mar. 8. 1994 to Takenaka discloses a ferroelectric capacitor process.
U.S. Pat. No. 5,675,184 entitled “Integrated Circuit Device” granted Oct. 7, 1997 to Matsubayashi et al. teaches a metal-insulator-metal (MIM) capacitor process in an Rf application. Thermoplastic material and magnetic substance layers are described.
SUMMARY OF THE INVENTION
The present invention describes a structure and method of fabricating copper metal-insulator-metal (MIM) capacitors and thick metal inductors simultaneously, using only one photolithography mask, for high frequency, mixed-signal or Rf, CMOS applications, in a dual damascene trench and via process.
The structure and process embodiments of this invention start with the first process step, the forming by damascene and chemical mechanical polishing (CMP) the first level inlaid metal structures. The process sequence is as follows: an insulating layer is deposited. This first insulating layer, e.g., silicon oxide, is patterned and reactive ion etched (RIE) upon a semiconductor substrate. The next processing step in building of the damascene structure, is the deposition by sputtering (PVD, physical vapor deposition) and patterning of a thin metal barrier layer (trench liner), e.g. Ta,TaN, and a thin copper seed layer. Copper metal is deposited upon the seed layer in the openings in insulator by electrochemical copper deposition (ECD). The excess copper metal is polished off and planarized with surface by chemical mechanical polishing (CMP) forming the first level metal for the capacitor bottom metal (CBM) layer.
Continuing with the summation of the structure and process embodiments of this invention, is the second step in this CMOS process, the deposition of a copper metal protecting “buffer layer”. This layer is needed to prevent copper corrosion with silicon oxide layers. It is deposited over the first level inlaid metal structures and first insulator layer. This buffer layer is, e.g., silicon nitride. The third process step is the blanket deposition of an intermetal dielectric (IMD) layer upon the buffer layer. This intermetal dielectric (IMD) is, e.g., silicon oxide, silicon nitride, or FSG fluoro-silicate glass, or PSG phosphosilicate glass. The fourth step is to form a photoresist masking layer by a lithography process, defining simultaneously both the metal-insulator-metal (MIM) capacitor and inductor area, over the first level of metal. Photoresist is coated and patterned upon the intermetal dielectric (IMD) layer. A reactive ion etch (RIE) is performed to etch the intermetal dielectric layer (IMD) layer, forming openings and stopping on the buffer layer.

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