Copper/low dielectric interconnect formation with reduced electr

Details Copper/low dielectric interconnect formation with reduced electr Copper/low dielectric interconnect formation with reduced electr

1999-01-26

2000-08-01

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438618, 438622, 438623, 438627, 438637, 438653, 438659, 438674, 438678, H01L 2144, H01L 214763

Patent

active

060966483

ABSTRACT:
A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.

REFERENCES:
patent: 5071518 (1991-12-01), Pan
patent: 5969422 (1999-10-01), Ting et al.
White et al, "Large Format Fabrication--A practical Approach to Low Cost MCM-D", IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part B, vol. 18, No. 1, Feb. 1995.

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