Copper damascene integration scheme for improved barrier layers

Details Copper damascene integration scheme for improved barrier layers Copper damascene integration scheme for improved barrier layers

2007-08-21

2007-08-21

Everhart, Caridad (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S021000, C438S653000

Reexamination Certificate

active

10834783

ABSTRACT:
A metal filled dual damascene structure with a reduced capacitance contribution and method for forming the same, the method including forming a first metal filled damascene lined with a first metal barrier layer thickness in a first dielectric insulating layer; and, forming a second metal filled damascene lined with a second metal barrier layer thickness overlying the first metal filled damascene in a second dielectric insulating layer.

REFERENCES:
patent: 6191025 (2001-02-01), Liu et al.
patent: 6191027 (2001-02-01), Omura
patent: 6306732 (2001-10-01), Brown
patent: 6448654 (2002-09-01), Gabriel et al.
patent: 6699783 (2004-03-01), Raaijmakers et al.
patent: 6919617 (2005-07-01), Yamada et al.
patent: 2004/0000719 (2004-01-01), Matsubara et al.
patent: 2004/0173910 (2004-09-01), Usami et al.

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