Copper alloy seed layer for copper metallization in an integrate

Details Copper alloy seed layer for copper metallization in an integrate Copper alloy seed layer for copper metallization in an integrate

1998-05-14

2000-05-23

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257753, 257762, 257764, 257765, H01L 2945

Patent

active

06066892&

ABSTRACT:
A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

REFERENCES:
patent: 5288665 (1994-02-01), Nulman
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5654232 (1997-08-01), Gardner
patent: 5744394 (1998-04-01), Iguchi et al.
patent: 5747360 (1998-05-01), Nulman
patent: 5770519 (1998-06-01), Klein et al.
patent: 5892282 (1999-04-01), Hong et al.
patent: 5900672 (1999-05-01), Chan et al.
patent: 5955785 (1999-09-01), Gardner et al.
patent: 5969422 (1999-10-01), Ting et al.
Murarka et al., "Copper Metallization for ULSI and Beyond", Critical Reviews in Soldi State and Materials Sciences, vol. 10, No. 2, pp. 87-124, 1995.
Gutman et al., "Integration of copper multilevel interconnects with oxide and polymer interlevel dielectrics," Thin Solid Films, vol. 270, No. 1/2, Dec. 1995, pp. 472-479.
Murarka et al., "Copper interconnection schemes: Elimination of the need of diffusion barrier/adhesion promoter by the use of corrosion resistant, low resistivity doped copper," Microelectronics Technology and Process Integration, Austin TX, USA, Oct. 20-21, 1994, Proceedings of the SPIE--The International Society for Optical Engineering, vol. 2335, 1994, pp. 80-90.
Murakata, et al. "Copper metallization for ULSI and beyond," Critical Reviews in Solid State and Materials Science, vol. 10, No. 2, 1995, pp. 87-124.
Lanford, et al. "Low-temperature passivation of copper by doping with Al or Mg," Thin Solid Films, vol. 262, 1995, pp. 234-241.

Affiliated with

Also associated with

Rating

Copper alloy seed layer for copper metallization in an integrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Copper alloy seed layer for copper metallization in an integrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Copper alloy seed layer for copper metallization in an integrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1839019