Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-22
2001-06-05
Whitehead, Jr., Carl (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S712000, C257S713000, C257S714000, C257S720000
Reexamination Certificate
active
06242778
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor chips; more specifically, it relates to the cooling of semiconductor chips fabricated in silicon on insulator technology.
BACKGROUND OF THE INVENTION
Since the development of integrated circuit technology, semiconductor chips have been fabricated on a mono-crystalline silicon wafer with active devices such as transistors and diodes fabricated near the top surface of the wafer. These chips often become very hot during operation, especially in the case of logic and microprocessor chips. Traditionally, the method for cooling these chips has been attachment of external heat sinks to the backside of the chip, or to the module into which the chip is packaged. This technology is often referred to as bulk silicon technology.
A more recent technology called silicon on insulator or SOI utilizes a very thin layer of mono-crystalline silicon stacked on top of an insulator, typically silicon oxide, which itself is stacked on top of a thick substrate, most often a silicon wafer. Several methods of fabricating such SOI wafers involve bonding together two wafers, each having an oxidized surface, oxidized surface to oxidized surface, to form the middle insulating silicon oxide, followed by thinning the backside of one of the wafers so as to form a very thin mono-crystalline silicon uppermost layer, with the other wafer becoming the lowermost layer of the stacked SOI wafer. The active devices are fabricated in the uppermost, very thin monocrystalline silicon layer of the stack.
Another feature of SOI technology is the ability to form isolated pockets of mono-crystalline silicon in the very thin mono-crystalline silicon layer by etching down to the middle insulating layer, and then back filling with an insulator such as silicon oxide, or by other methods.
In this newer technology, cooling still utilizes the methods applied to conventional chips fabricated with bulk silicon technology. One problem with the existing cooling techniques, however, is that the heat generated from any individual device or group of devices must travel from the device junctions through the bulk silicon to the backside of the chip where the heatsink can conduct the heat away. The effectiveness of cooling a single device or group of devices is affected by the cooling of the chip as a whole. For SOI, added to this problem is the fact that SOI devices are generally designed to run faster and can generate more heat. If the heat could be conducted away directly at or very near to the device junctions, individual devices or groups running very hot could be cooled more effectively.
With more specific reference to the prior art, U.S. Pat. No. 4,794,092 to Solomon, teaches a method of joining two wafers together using two oxidized wafers, where one or more of the wafers have trenches etched into the surfaces to be joined. These trenches which may or may not be filled with insulating materials (if the trenches are not filled in wafer form, they are filled after dicing), are formed in the street or kerf regions of the wafer. During subsequent dicing operations, silicon at the edges is not exposed due to the insulating material.
U.S. Pat. No. 5,091,330 to Cambou et. al, describes a method of forming islands of monocrystalline silicon in SOI wafers. Trenches are formed in the top of a first mono-crystalline silicon wafer and filled with an insulator. A second silicon wafer having an oxidized surface is joined to this surface by dielectric bonding. The backside of the first wafer is then polished until the mono-crystalline silicon islands are exposed.
U.S. Pat. No. 4,954,458 to Reid teaches a method of cooling a bulk technology chip by etching channels into the backside of the chip, attaching a plate to cover the top of the channels and then forcing cooling fluid through the channels. In this method the cooling channels are located a significant distance from the device junctions, leaving a significant amount of silicon between the channels and the device junctions. The process as described would not be capable of etching extremely fine lines from the backside of the wafer to the junctions of individual devices. Further, stopping at a precise distance from device junctions would be most difficult.
The present invention is directed to providing a method of providing heat sinking at or very near to the device junctions in chips fabricated in SOI technology.
SUMMARY OF THE INVENTION
It is an object of the present invention to describe a structure and provide a method of fabricating the structure for cooling individual semiconductor devices or groups of devices fabricated in SOI technology by locating cooling channels substantially under selected individual semiconductor devices or groups of devices, the channels separated by the insulating layer of the SOI technology from the semiconductor devices.
It is a further object of the present invention to describe a structure and provide a method of fabricating the structure for cooling regions of an SOI chip containing groups of semiconductor devices fabricated in SOI technology by locating cooling channels substantially under selected regions of the chip, the channels separated by the insulating layer of the SOI technology from semiconductor devices in the selected portions of the chip.
It is a still further object of the present invention to describe a method of providing coolant fluid to the cooling channels.
It is another object of the present invention to describe a structure and provide a method of fabricating the structure for cooling individual semiconductor devices or groups of devices fabricated in SOI technology by locating thermal conductors substantially under selected individual semiconductor devices or groups of devices, the thermal conductors separated by the insulating layer of the SOI technology from the semiconductor devices.
It is still another object of the present invention to describe a structure and provide a method of fabricating the structure for cooling regions of an SOI chip containing groups of individual semiconductor devices fabricated in SOI technology by locating thermal conductors substantially under selected regions of the chip, the thermal conductors separated by the insulating layer of the SOI technology from the semiconductor devices in the selected portions of the chip.
It is an additional object of the present invention to describe a structure of and method for attaching a heat sink to such thermal conductors.
REFERENCES:
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4761681 (1988-08-01), Reid
patent: 4794092 (1988-12-01), Solomon
patent: 4954458 (1990-09-01), Reid
patent: 5034688 (1991-07-01), Moulene et al.
patent: 5091330 (1992-02-01), Cambou et al.
patent: 5099311 (1992-03-01), Bonde et al.
patent: 5099910 (1992-03-01), Walpole et al.
patent: 5146314 (1992-09-01), Pankove
patent: 5218515 (1993-06-01), Bernhardt
patent: 5239200 (1993-08-01), Messina et al.
patent: 5258887 (1993-11-01), Fortune
patent: 5265670 (1993-11-01), Zingher
patent: 5316075 (1994-05-01), Quon et al.
patent: 5388635 (1995-02-01), Gruber et al.
patent: 5777365 (1998-07-01), Yamaguchi et al.
Marmillion Patricia McGuinness
Palagonia Anthony Michael
Pierson Bernadette Ann
Schmidt Dennis Arthur
Berezny Neal
International Business Machines - Corporation
Jr. Carl Whitehead
Sabo William D.
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