Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-08-04
2001-09-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S210130, C365S189050, C365S189070, C365S233100
Reexamination Certificate
active
06288959
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to power management in a memory system that, e.g., includes a dynamic random access memory (DRAM) array in a static random access memory (SRAM) interface. In particular, the present invention relates to reducing power consumption in a memory system by controlling the precharge cycle.
BACKGROUND
Power consumption and form factors in portable systems, such as mobile phones, third-generation (3-G) wireless systems, and personal digital assistants (PDA), are a significant concern, particularly due to the desire to increase battery life and reduce size. Memory devices within portable systems are a significant part of the total power consumption. Typically, SRAM arrays are more power efficient than DRAM arrays and, thus, are conventionally used in portable systems. DRAM arrays, however, are typically more dense than SRAM arrays and thus DRAM arrays have a smaller form factor. The memory size used in portable systems is growing, i.e., currently the typical memory size is 4 Mbit but will soon be 8 Mbit. Thus, the increased density of DRAM arrays will be desirable for use in mobile communication systems.
One type of memory device that has been discussed as a possible replacement of SRAMs for portable systems is known as “pseudo SRAM.” Pseudo SRAM uses a non-multiplexed SRAM type interface with a DRAM core. Advantageously, the SRAM type interface requires less power than a conventional multiplexed address DRAM interface. Thus, pseudo SRAM provides a small form factor because of the DRAM core and yet provides some power savings because of the SRAM interface. Unfortunately, a major drawback to pseudo SRAM is that the DRAM core consumes more power than an SRAM core. Thus, it is desirable to reduce the power consumption of a DRAM core in pseudo SRAM.
SUMMARY
A memory system with a DRAM array in a non-multiplexed address, SRAM type, interface is precharged only when a new word line is asserted, in accordance with the present invention. When the word line is not changed, the DRAM is not precharged, thereby reducing power consumption. The precharge cycle occurs prior to the active cycle so that the memory system can determine whether the precharge operation is necessary. In addition, a dummy precharge circuit is used to simulate a precharge cycle for timing purposes. Thus, the active cycle is performed at the end of the simulated precharge cycle so that the timing of the active cycle will be consistent from one cycle to the next regardless of whether the DRAM is precharged. When the DRAM is precharged, the actual precharge operation has the same timing as the simulated precharge cycle.
Thus, one embodiment of the present invention includes a method of operating a DRAM array having a plurality of memory cells arranged in rows with associated x-addresses and columns with associated y-addresses, that includes receiving a first address containing at least an x-address and a y-address and receiving a second address containing at least a new x-address and a new y-address and determining if the new x-address is different than the x-address in the first address. The method includes precharging the DRAM array if the new x-address is different than the x-address in the first address and not precharging the DRAM array if the new x-address is not different than the x-address in said first address. The precharge cycle precedes the active cycle, and thus, the DRAM is accessed according to the second address after precharging said DRAM array. In addition, a dummy precharge timing cycle is generated for timing purposes.
The method of operation of the memory system includes receiving a new address for the DRAM array, performing a precharge cycle to precharge the DRAM array when the new address includes a new word line, and performing an active cycle to access the DRAM array after the precharge cycle.
The memory system of the present invention includes a control circuit for controlling the operation of a DRAM array. The control circuit, e.g., includes an activity monitor circuit and a timing control circuit. The control circuit receives an x-address associated with the word line for a new operation cycle, and includes a comparison circuit that determines if the x-address is different from a preceding x-address for a preceding operation cycle. The control circuit also includes a timing generator coupled to the comparison circuit and that outputs the precharge signals, including an equalization enable signal and a sense latch disable signal, when the x-address is different from the preceding x-address and outputs an equalization disable signal and a sense latch enable signal when the x-address is the same as the preceding x-address.
With the use of the control circuitry including the timing control circuit that activates the precharge circuitry only when there is a new word line address, a significant power savings may be obtained. In addition, the control circuitry may receive the new bit line address, which is compared to the preceding bit line address. If a different bit line address is being asserted, the control circuitry will enable a sense latch circuit for the bit lines. If, however, the bit line address is the same as the preceding address, the sense latch circuit may be disabled, thereby further reducing power consumption.
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Liusie Donald
Ouyang Paul H.
DMEL Incorporated
Halbert Michael J.
Lam David
MacPherson Alan H.
Nelms David
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