Controlling output current rambus DRAM

Details Controlling output current rambus DRAM Controlling output current rambus DRAM

2001-12-31

2003-05-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020, C365S230050

Reexamination Certificate

active

06567317

ABSTRACT:

BACKGROUND
1. Field of Invention
The inventions described herein relate in general to circuits for controlling an output current of a Rambus DRAM. More particularly, they relate to an output current control circuit enabling reduction of circuit area and current consumption compared with known devices.
2. General Background and Related Art
FIG. 1
(Prior Art) is a block diagram of a known circuit arrangement for controlling output driving of a Rambus DRAM. An output current controller
10
produces a current control signal ictrl <0:6> that controls a current flow of an output driver by increasing or decreasing a current control counter. This is accomplished by measuring actual voltage levels VOH and VOL from a data port DQA. A gate voltage generator, VTG GNR
11
produces a gate voltage Vgate as a new voltage level. A gate voltage distributor
12
provides an upper device of the output driver with a voltage envg <0:6> attained by multiplexing a time clock enabling signal tclk enable and the current control signal ictrl <0:6> generated from voltage generator
11
in accordance with the gate voltage Vgate generated from voltage generator
11
. A slew-rate controller
13
produces control codes sl
1
and sl
2
specifying a slew rate of an output regardless of power, voltage, and temperature. A phase splitter
14
generates clocks tclk
1
and tclk
1
b having 180° difference from one another and based on an input time clock tclk. A MUX/predriver
15
outputs input data eread and oread, which are synchronized with the clocks tclk
1
and tclk
1
b output from the phase splitter
14
, to an output driver
16
in the form of voltages q and q
1
to output driver
16
, constituting a lower device of the output driver in accordance with the control codes sl
1
and sl
2
provided by the slew rate controller
13
. Output driver
16
provides a pad PAD with a an appropriate current by providing a pull-down path of a Rambus signal logic(RSL) by turning on/off N-type MOS transistors in accordance with the voltage envg<0:6> distributed by the gate voltage distributor
12
and the voltages q and q
1
output from the MUX/predriver
15
.
In the output current controller
10
at an initial stage of active operation, actual current levels are measured from a pair of input pads DQA<4> and DQA<3>(not shown in the drawing) respectively. A count value is then decreased the output current control counter if the measured current levels are higher than a specific value, or the count value is then increased if the measured current levels are lower than the specific value. Thus, the output current controller
10
outputs the output current control signal ictrl<0:6>, which adjusts the number of turned-on transistors of the output driver
16
so as to satisfy an output current flow of the output driver
16
, to the gate voltage distributor
12
.
A time clock enabling signal tclk enable is input to the gate voltage distributor
12
from an external input. In this case, the gate voltage generator
11
provides the gate voltage distributor
12
with a gate voltage Vgate which is a voltage having a new level as a source power. Ultimately, the gate voltage distributor
12
receives the output current control signal ictrl <0:6> output from the output current controller
10
, the time clock enabling signal tclk enable, and the gate voltage Vgate output from the voltage generator
11
. The gate voltage distributor
12
multiplexes the current control signal ictrl <0:6> and time clock enabling signal tclk enable received by the output current controller
10
, selects and outputs the gate voltage Vgate or a ground voltage VSS enabling to adjust the turning-on number in accordance with the multiplexed value, and then outputs it to the output driver
16
.
FIG. 2
(Prior Art) is a schematic diagram including detailed circuits of the gate voltage distributor
12
and the output driver
16
shown in
FIG. 1
(Prior Art). A Vgate voltage as a new voltage, which is produced by carrying out comparison and amplification on a reference voltage Vgref input to an inverting input (−) of an operational amplifier OP
1
and a voltage input to a non-inverting input terminal (+) by being fed back from an output terminal, is output to an inverter I
1
. In this case, a NAND gate ND
1
carries out a NAND operation on the current control signal ictrl <0:6> output from the current controller
10
and the time clock enabling signal tclk_enable and then provides the inverter I
1
with them. The inverter I
1
then inverts the output signal from NAND gate ND
1
in a manner that the output driver
16
is provided with the gate enabling signal envg <0:6> having a gate voltage level using the gate voltage Vgate output from amplifier OP
1
as a source if the signal output from the NAND gate ND
1
is low or the gate enabling signal envg <0:6> having a ground voltage level using the ground voltage VSS as a source if the signal output from the NAND gate ND
1
is high. Therefore, lower transistors Tr
1
to Trn of the output driver
16
are turned on as many as the number of the gate enabling signals envg having the gate voltage level output from the inverter I
1
.
Receiving a time clock tclk form outside, the phase splitter
14
produces a pair of clocks tclk
1
and tclkb having a 180° phase difference (see
FIG. 1
) and then provides the MUX/predriver
15
with the clocks tclk
1
and tclkb. Even and odd data are input to the MUX/predriver
15
from outside. The slew-rate controller
13
(see
FIG. 1
) outputs the control codes sl
1
and sl
2
to the MUX/predriver
15
so as to fix a slew rate of an output regardless of power, voltage, and temperature. Therefore, the MUX/predriver
15
transmits the even data to the output driver
16
if receiving the clock tclk
1
from the phase splitter
14
or the odd data to the output driver
16
if receiving the other clock tclk
1
b having a different phase (180° from tclk
1
).
Receiving the control codes sl
1
and sl
2
(shown in
FIG. 1
) from the slew-rate controller
13
, the MUX/predriver
15
outputs the control voltages q and q
1
to the output driver
16
so as to turn on/off the lower device of the output driver
16
such as the lower transistors. Transistors Tr
1
to Trn as the upper device of the output driver
16
are turned on as many as the number adjusted by the output voltage envg <0:6> of the gate voltage distributor
12
, while the other transistors T
1
to Tn and Q
1
to Qn as the lower device of the output driver
12
are turned on by the MUX/predriver
15
so as to form a pull-down path.
Capacitors ‘C
1
’ and ‘C
2
’ of the output driver
16
are decoupling capacitors preventing noise coupling. The upper and lower transistors become turned on so as to supply the corresponding pad with a satisfactory output current by adjusting an output of RSL (Rambus signaling level), that is a swing width, and carry output data on a channel.
Generally, a command, so-called current control, is carried out periodically in a Rambus DRAM so as to maintain a constant output current at a data port. The data port in Rambus DRAM is constructed with 8 bit buses DQA[7:0] and DQB[7:0] (not shown in FIG.
2
). A known output current control circuit for controlling currents output from the data ports DQA[7:0] and DQB[7:0] constantly is explained by referring to
FIG. 3
as follows.
FIG. 3
is a block diagram of the output current controller
10
shown in FIG.
1
. An enabling signal CCEval becomes active (‘high’ when a ‘current control command’ is applied to a Rambus DRAM from a controller (not shown in the drawing). The output current controller
10
includes a first current detector
31
outputting a signal CClncrA having a ‘low’ value if a current flow received from a couple of the data ports (not shown in the drawing) DQA<4> and DQA<3> by the enabling signal CCEval is higher than a target value through a comparison therebetween or a signal CClncrA having a ‘high’ value if the curre

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