Controlling improvement of critical dimension of dual...

Details Controlling improvement of critical dimension of dual... Controlling improvement of critical dimension of dual...

1999-03-19

2001-09-04

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S631000, C438S633000, C438S637000, C438S638000, C438S640000

Reexamination Certificate

active

06284645

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of writing structures in integrated circuit devices. More particularly, the present invention relates to the formation of vias, contacts and wiring lines by using a dual damascene process spin-on-glass materials.
2. Description of the Prior Art
Some specific structures, that are semiconductor highly integrated circuits utilize multilevel wiring line structures, usually for interconnecting regions within devices. Also this arrangement is for interconnecting one or more devices within the integrated circuits. Conventionally such an arrangement provides the first or lower level wiring lines or interconnect structures and then form a second level wiring line in contact with the first level wiring lines or interconnect structures.
FIG. 1A
shows a semiconductor substrate
100
formed firstly and then silicon oxide layer
101
is deposited onto the substrate
100
using PECVD method. Sequentially, shown in
FIG. 1B
, silicon nitride layer
102
is then deposited upon the silicon oxide layer
101
, by applying PECVD method as well. Next,
FIG. 1C
a silicon oxide layer
103
is deposited on the silicon nitride
102
. Consequentially a pattern of metal lines is transferred and defined on the silicon nitride
102
and the silicon oxide layer
103
. Then the silicon nitride
102
and the silicon oxide layer
103
are removed to form a multitude of openings for metal lines, shown as FIG.
1
D. Next, depicted in
FIG. 1E
, a photoresist layer
104
is blanket formed on the silicon oxide layer
101
and the surface and side walls of the silicon oxide layer
103
. Another pattern is first transferred onto the photoresist layer
104
and thereafter the silicon oxide layer
101
is partially removed to form a multitude of vias, shown in FIG.
1
F. According to the above process, the critical dimension will very thick and therefore it also will seriously effect whole processing.
Commonly, the photoresist layer should be formed thicker for using and owning a long depth of focus in order to expose the entire thickness of the photoresist mask. However, for use of steppers that need high solution, it is difficult in forming quite deep focus in the process. Also it makes thick critical dimension happening and reduces reliability of production.
Interconnections are typically formed between the first level wiring line or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This will be accomplished through the second level of wiring lines.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming integrated circuit devices that substantially achieves estimated semiconductor devices completely.
In one embodiment, a substrate is first provided and an interlayer dielectric layer is formed over the substrate. Then an etch stop layer is formed and the etch stop layer is patterned. Sequentially a coating layer is formed and a photoresist mask is formed and defined. Consequentially, the photoresist mask and the spin-on-glass layer are all removed. Then a metal layer is deposited. Finally both the following processes for removing excess metal and planarizing the surface of integrated circuit device are carried out.
Apparently the photoresist layer should be formed thicker for using and owning a long depth of focus in order to expose the entire thickness of the photoresist mask according to the present invention. As applied to steppers that do not need high solution, it is much easier in forming a very deep focus in the process. Also this makes thin critical dimension happen and increases reliability of production.


REFERENCES:
patent: 5880018 (1999-03-01), Boeck et al.
patent: 6004883 (1999-12-01), Yu et al.
patent: 6204096 (2001-03-01), Lai et al.

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