Controlled gate length and gate profile semiconductor device

Details Controlled gate length and gate profile semiconductor device Controlled gate length and gate profile semiconductor device

2000-01-29

2002-08-13

Jackson, Jr., Jerome (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S336000, C257S412000

Reexamination Certificate

active

06433371

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to manufacturing semiconductors and more specifically to a manufacturing method for Metal-Oxide-Semiconductors (MOS) which employ lightly doped drain (LDD) structures.
BACKGROUND ART
Complementary Metal-Oxide-Semiconductor (CMOS) is the primary technology for ultra large-scale integrated (ULSI) circuits. These ULSI circuits combine two types of Metal-Oxide-Semiconductor (MOS) devices, namely P-channel Metal-Oxide-Semiconductor (PMOS) devices and N-channel Metal-Oxide-Semiconductor (NMOS) devices, on the same integrated circuit. To gain performance advantages, scaling down the size of MOS devices has been the principal focus of the microelectronics industry over the last two decades.
The conventional process of manufacturing MOS devices involves doping a semiconductor substrate and forming a gate oxide layer on the substrate followed by a deposition of polysilicon. A photolithographic process is used to etch the polysilicon to form the device gate. As device sizes are scaled down, the gate width, source/drain (S/D) junctions have to scale down. As the gate width reduces, the channel length between the source and drain is shortened. The shortening in channel length has led to several severe problems.
One of the problems associated with shortened channel length is the so-called “hot carrier effect”. As the channel length is shortened, the maximum electric field E
m
becomes more isolated near the drain side of the channel causing a saturated condition that increases the maximum energy on the drain side of the MOS device. The high energy causes electrons in the channel to become “hot”. The electron generally becomes hot in the vicinity of the drain edge of the channel where the energy arises. Hot electrons can degrade device performance and cause breakdown of the device. Moreover, the hot electrons can overcome the potential energy barrier between the semiconductor substrate and the silicon dioxide layer overlying the substrate, which causes hot electrons to be injected into the gate oxide layer.
Problems arising from hot carrier injections into the gate oxide layer include generation of a gate current and generation of a positive trapped charge which can permanently increase the threshold voltage of the MOS device. These problems are manifested as an undesirable decrease in saturation current, decrease of the transconductance and a continual reduction in device performance caused by trapped charge accumulation. Thus, hot carrier effects cause unacceptable performance degradation in MOS devices built with conventional drain structures when channel lengths are short.
Reducing the maximum electric field, E
m
, in the drain side of the channel is a popular way to control the hot carrier injections. A common approach to reducing E
m
is to minimize the abruptness in voltage changes near the drain side of the channel. Disbursing abrupt voltage changes reduces E
m
strength and the harmful hot carrier effects resulting therefrom. Reducing E
m
occurs by replacing an abrupt drain doping profile with a more gradually varying doping profile. A more gradual doping profile distributes E
m
along a larger lateral distance so that the voltage drop is shared by the channel and the drain. Absent a gradual doping profile, an abrupt junction can exist where almost all of the voltage drop occurs across the channel. The smoother or more gradual the doping profile, the smaller E
m
is which results in lesser hot carrier injections.
To try to remedy the problems associated with hot carrier injections, alternative drain structures such as lightly doped drain (LDD) structures have been developed. LDD structures provide a doping gradient at the drain side of the channel that lead to the reduction in E
m
. The LDD structures act as parasitic resistors to absorb some of the energy into the drain and thus reduce maximum energy in the channel. This reduction in energy reduces the formation of hot electrons. To further minimize the formation of hot electrons, an improvement in the gradual doping profile is needed.
In most typical LDD structures of MOS devices, S/D junctions are formed by two implants with dopants. One implant is self-aligned to the polysilicon gate to form shallow S/D extension junctions. An oxide or oxynitride implant spacer then is formed around the polysilicon gate. With the shallow S/D extension junctions protected by the implant spacer, a second implant with a heavier dose is self-aligned to the implant spacer to form deep S/D junctions. There would then be a rapid thermal anneal (RTA) of the S/D junctions to enhance the diffusion of the dopants so as to optimize the device performance. The purpose of the first implant is to form an LDD at the edge of the polysilicon gate near the channel. In an LDD structure, almost the entire voltage drop occurs across the lightly doped drain region. The second implant with heavier dose forms low resistance deep S/D junctions, which are coupled to the LDD structures. Since the second implant is spaced from the channel by the implant spacer, the resulting drain junction adjacent to the light doped drain region can be made deeper without impacting device operation. The increase junction depth lowers the sheet resistance and the contact resistance of the drain.
In most typical LDD structures for CMOS devices, S/D junctions are formed by four implants with dopants, each implant requiring a masking step. The four masking steps are: a first mask (a P-LDD mask) to form the P-LDD structures, a second mask (an N-LDD mask) to form the N-LDD structures, a third mask (a P+S/D mask) to form the P-type doped, deep S/D junctions, and a fourth mask (an N+S/D mask) to form the N-type doped, deep S/D junctions. Each masking step typically includes the sequential steps of preparing the semiconductor substrate, applying a photoresist material, soft-baking, patterning and etching the photoresist to form the respective mask, hard-baking, implanting a desired dose of a dopant with the required conductivity type, stripping the photoresist, and then cleaning of the substrate. These processing steps associated with each masking step adversely increase cycle time and process complexity and also introduce particles and defects, resulting in an undesirable increase in cost and yield loss. Hence, there is a need to provide a method for forming MOS devices and CMOS devices with LDD structures that lessens the number of masking steps required.
Further improvements in transistor reliability and performances for exceeding smaller devices are achieved by a transistor having LDD structures only at the drain region (asymmetric LDD structures). Parasitic resistance due to the LDD structure at the source region of a transistor causes a decrease in drain current as well as greater power dissipation for a constant supply voltage. The reduction in drain current is due to the effective gate voltage drop from self-biased negative feedback. At the drain region of the transistor, the drain region parasitic resistance does not appreciably affect drain current when the transistor is operating in the saturation region. Therefore, to achieve high-performance MOS transistor operation, it is known to form LDD structures only at the drain regions but not at the source regions.
One significant problem with the LDD structures is the formation of parasitic capacitors. These parasitic capacitors are formed due to the diffusion of dopants from the LDD towards the channel underneath the polysilicon gate as a result of RTA and other heating processes in the manufacturing of the transistors. These parasitic capacitors are highly undesirable because they slow down the switching speed of the transistors. The adverse speed impact increases disproportionately with shortened channels. Basically, the parasitic capacitance due to LDD structures as a percentage of the total transistor capacitance is higher for sub-0.18 micron transistors than it is for a 0.18-micron transistor and even worse for a sub-0.13 transistor, making the adverse speed impact much

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