Controlled faceting of source/drain regions

Details Controlled faceting of source/drain regions Controlled faceting of source/drain regions

2005-09-20

2005-09-20

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S752000

Reexamination Certificate

active

06946350

ABSTRACT:
Numerous embodiments of a method for highly selective faceting of the S/D regions in a CMOS device are described. In one embodiment, source/drain regions are formed on a substrate. The source/drain regions are wet etched to form faceted regions. A silicon germanium layer is formed on the faceted regions of the source/drain regions to yield a strained device.

REFERENCES:
patent: 6235568 (2001-05-01), Murthy et al.
patent: 6495402 (2002-12-01), Yu et al.
patent: 6599803 (2003-07-01), Weon et al.

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