Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-08-21
2007-08-21
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C365S225000
Reexamination Certificate
active
11420454
ABSTRACT:
The invention is an electronic circuit designed for incorporation on computer memory modules such as DDR DIMMs. It couples control signals such as address bits, bank selects, enable and even clock signals between the module input connector and the memory devices. The circuit provides low propagation delay, fast rise and fall times with no overshoot or undershoot, and significantly improves timing control compared to memory modules of the present art. Capacitive loading on the motherboard is typically much less than that provided by a single memory device input and is independent of the number of memory devices per bank or the number of banks of memory devices on the memory module. For multiple memory modules connected to the memory bus, capacitive loading is essentially N times the equivalent loading for a single memory module.
REFERENCES:
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 6292405 (2001-09-01), Nicosia et al.
patent: 6314037 (2001-11-01), Shiomi et al.
McClanahan Robert F.
Washburn Robert D.
Harriman, II J. D.
Hoang Huan
Thunder Creative Technologies, Inc.
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