Control of oxide thickness in vertical transistor structures

Details Control of oxide thickness in vertical transistor structures Control of oxide thickness in vertical transistor structures

2000-04-20

2002-04-16

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S149000, C438S210000, C438S244000, C156S922000

Reexamination Certificate

active

06372567

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a process for providing oxide thickness control in vertical transistor structures used in DRAMs (dynamic random access memory) that require gate oxides with optimum oxide thickness, wherein, at the same time, planar transistors present on the driver and support circuits on the DRAM chips need oxides that are also optimized in accordance with driver and support circuit needs.
2. Description of Related Art
DRAM memory chip area optimization requires incorporation of the transistor into the capacitor trench side wall. This optimization technology reduces the required chip size. Nevertheless, the gate of the array transistor must me placed simultaneously on different crystal planes inside of the trench side wall, and it has been found that the gate oxide thickness is strongly affected by the crystal orientation.
Therefore, the problems confronted by DRAM memory chip area optimization to incorporate the transistor into the capacitor trench side wall, wherein the process normally entails a reduction in the required chip size is: that the thickness of the oxide layer on the vertical side wall is usually thicker in relation to the oxidation (oxide layer) on the wafer surface; and the oxidation rate is dependent upon the crystal orientation of planes on the trench side wall.
U.S. Pat. No. 5,183,775 discloses a method for forming a capacitor in a trench of a semiconductor wafer by implantation of trench surfaces with oxygen. The process entails: selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top comers of the trench into regions of the wafer adjacent the surfaces at the top comers of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench causes the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.
A process for fabricating stacked trench capacitors of dynamic ram is disclosed in U.S. Pat. No. 5,026,659. The process entails: forming trenches between transistor gate electrodes and growing a thermal oxide film for preventing current leakage through side walls of the trench; ion implanting a bottom of the trench with dopants of an opposite conductivity type to those of a transistor source or drain gradient for preventing current leakage through the trench bottom; forming a side-spacer silicon layer on a side wall of the trench by depositing a first silicon layer thereon and performing an anisotropic reactive ion etch on the side-spacer silicon layer; performing wet etch on the thermal oxide film which is unprotected by the side-spacer silicon layer and then depositing a subsequent silicon layer for a storage node of the capacitor; and forming a dielectric layer and capacitor plate.
U.S. Pat. No. 4,942,554 disclose a three-dimensional, one-transistor cell arrangement for dynamic semiconductor memories comprising a trench capacitor and a method of manufacturing the same. The capacitor for the charges to be stored is created as a trench capacitor in the substrate. The first electrode is formed by the substrate and the second electrode that stores the charges is formed by doped polycrystalline silicon that fills the trench. The capacitor, separated by an insulating layer, is arranged under the field effect transistor (selection transistor). An insulated gate electrode (transfer electrode/word line) that lies at the surface of the substrate, is arranged having source/drain zones generated in the recrystallized silicon layer applied on the insulating layer and is connected to the source/drain zones thereof via an electrically conductive contact.
A method for forming trenches in a silicon layer of a substrate in high-density plasma processing system is disclosed in U.S. Pat. No. 5,935,874. The plasma processing system has a variable plasma generation source and a variable ion energy source with the variable plasma generation source being configured to be controlled independently of the variable ion energy source. The method further includes flowing an etchant source gas that includes O
2
, helium, and at least one of SF
6
and NF
3
into the plasma-processing chamber. There is also included energizing both the variable plasma generation source and the variable ion energy source to form a plasma from the etchant source gas. Additionally, there is included employing the plasma to etch the trench.
In the formation of DRAM memory chip area optimization that requires the incorporation of the transistor into the capacitor trench side wall, and wherein this process reduces the required chip size, and wherein the gate of the array transistor must be placed simultaneously on different crystal planes inside the trench side wall, there is a need to resolve the problem where the thickness of the oxide layer on the vertical side wall is thicker in comparison to the oxidation (oxide layer) on the wafer surface and to resolve the problem due to the fact that the oxidation rate depends on the crystal orientation of planes on the trench side wall.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a process to over come the fact that the thickness of an oxide layer on a vertical side wall is thicker compared to the thickness of oxide layers on the wafer surface upon incorporation of a transistor into the capacitor trench side wall, upon preparation of vertical transistor structures in DRAMs.
A further object of the present invention is to provide a process to over come the fact that the oxidation rate depends upon the crystal orientation of planes on the trench side wall in preparing vertical transistor structures in DRAMs.
A yet further object of the present invention is to provide an integrated or combined process innovation scheme when preparing vertical transistor structures in DRAMs to control oxide thickness in vertical transistor structures in DRAMs to obtain homogeneously thick oxides of the required target thickness on the trench side wall at all different crystal planes inside the trench.
In general, the invention is accomplished by: using a plasma to effect amorphization of the capacitor trench side walls followed by thermal oxidation to obtain homogenous gate oxidation at all different crystal planes inside the trench. Plasma ion implantation (PLAD) is used to create a uniform, very thin amorphous layer at the vertical trench side wall by ion bombardment and subjecting the formed amorphous layer to heat in an oxidizing atmosphere to affect oxidation and recrystallization of the amorphous layer.


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patent: 5935874 (1999-08-01), Kennard
patent: 6177299 (2001-01-01), Hsu et al.
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