Control of backgate bias for low power high speed CMOS/SOI devic

Details Control of backgate bias for low power high speed CMOS/SOI devic Control of backgate bias for low power high speed CMOS/SOI devic

1991-06-17

1993-02-09

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257365, 257369, 257901, 437 21, 437 34, 437 40, 437 84, H01L 2701

Patent

active

051855356

ABSTRACT:
Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.

REFERENCES:
patent: 4996575 (1991-02-01), Ipri et al.
patent: 5103277 (1992-04-01), Caviglia et al.

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