Control input timing-independent dynamic multiplexer circuit

Details Control input timing-independent dynamic multiplexer circuit Control input timing-independent dynamic multiplexer circuit

2000-02-29

2001-03-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230020, C365S189050

Reexamination Certificate

active

06198666

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an output multiplexer (MUX) for a high speed memory and, more particularly, to an output MUX having an output interlock circuit which ensures that only one data signal can be present on the output line at a time regardless of whether or not a control signal for the next data cycle transitions during this same time.
2. Description of the Related Art
Static random access memory (SRAM) is a type of high speed memory wherein each bit is represented by the state of a circuit with two stable states. Such a “bistable” circuit can be built with four transistors (for maximum density) or six (for highest speed and lowest power). SRAM retains data bits in its memory as long as power is being supplied. Unlike dynamic RAM (DRAM), which stores bits in cells made up of a capacitor and a transistor, SRAM does not have to be periodically refreshed. Static RAM provides faster access to data but is more expensive than DRAM. SRAM is commonly used for a computer's level two (L2) cache memory. The function of the L2 cache is to stand between DRAM and a computer's central processing unit (CPU), offering faster access than DRAM.
SRAM memory cells are typically configured in arrays and addressable subarrays. An output multiplexer (MUX) receives the data from the SRAM subarrays and multiplexes the data onto the data bus for the CPU. Unfortunately, due to manufacturing considerations as well as the physical placement within the SRAM array, not all of the subarrays are accessible at the same speed. That is, some of the subarrays are accessible faster and some are slower than others. The array data therefore has non-uniform timing relations as compared to the SRAM clock due to a large skew associated with addressing the fastest and then the slowest subarrays in the memory.
These non-uniform timing relations result in a critical timing bottleneck the becomes more pervasive with the increasing speed of the memory device. This situation leaves a very small window for the MUX control inputs to transition between the reset of the slowest data and prior to the fastest data. Furthermore, it leaves little if any margin to increase frequency (i.e., the faster the frequency the smaller the timing window becomes).
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an output multiplexer(MUX) circuit to be placed between the SRAM array output and the CPU data bus to negotiate timing skews created by subarrays of differing speeds.
It is yet another object of the present invention to provide an output multiplexer which guarantees a single SRAM data on the output line at a given time even if the a control line for the next memory cycle transitions during this time without handshaking with the SRAM.
According to the invention an output MUX is provided with an interlock circuit to insure that only one data bit can be on the output line at a given time. A plurality of data lines are switched, one at a time, onto a single output line by switching transistors in response to one of a plurality of control inputs. A pair of cross-coupled NAND gates are connected to the output line to produce a LOCK signal whenever data is detected on the output line. The LOCK signal is logically NANDed with each of the control inputs prior to reaching the switching transistors. In this manner, the control signals are effectively locked out and not allowed to propagate through to the switching transistors while the output line is already being driven by data. A delay loop connected to the output line resets the output line via a pull-up transistor. Even when the output line is reset, the LOCK signal remains active (low) due to the pair of cross-coupled NAND gates. As long as the LOCK signal remains active any of the control inputs may switch without causing any glitches or fails on the output line. When the active data line becomes inactive, a logic gate resets the pair of cross coupled NAND gates and disarms the LOCK signal in preparation for the next memory cycle MUXing.
Thus, the window in which a control signal on the control line may transition is considerably broadened by the elimination of one of the timing prerequisites of the MUX control signals. As a result, these control signals may transition anytime prior to the array data for the fastest subarray and thus eliminate cycle time dependencies.


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