Control circuit of an output buffer

Details Control circuit of an output buffer Control circuit of an output buffer

1997-09-19

1999-05-18

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523002, 36518902, 365194, 365191, G11C16/04

Patent

active

059056789

ABSTRACT:
The invention relates to a control circuit for an output buffer, of the type which comprises a first input terminal receiving a first enable signal and a second input terminal receiving a second enable signal, as well as first and second output terminals to generate first and second partial enable signals to transfer discrete sets of data bits. The first and second input terminals are coupled to the first and second output terminals through a multiplexer. The control circuit includes a synchronization circuit for linking the partial enable signals operatively to a synchronization signal of the pulse type being synchronous with the loading of the output buffer. The synchronization circuit is connected between an output terminal of the multiplexer and the first and second output terminals of the control circuit.

REFERENCES:
patent: 4825410 (1989-04-01), Lee
patent: 5268868 (1993-12-01), Kajigaya et al.
patent: 5307317 (1994-04-01), Shiraishi et al.
patent: 5768215 (1998-06-01), Kwon et al.

Affiliated with

Also associated with

Rating

Control circuit of an output buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control circuit of an output buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control circuit of an output buffer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1765080