Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-10
2003-05-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06567964
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-8757, filed Feb. 21, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
This invention relates to the design, layout, testing and manufacture of integrated circuits, and more particularly to systems, methods and computer program products for generating mask data for integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are widely used in consumer and commercial applications. As is well known to those having skill in the art, integrated circuits generally include multiple layers in and/or on an integrated circuit substrate. These layers may include semiconductors, conductors, insulators and/or combinations of these and/or other materials. The layer may be fabricated, for example, by blanket forming a layer and then patterning the blanket-formed layer. The layer may be blanket formed using sputtering, deposition, spin coating and/or other conventional methods. Patterning may be performed by transferring patterns that are defined in a physical design or layout to the actual physical layer. The physical designs may be represented by computer data corresponding to two-dimensional shapes. The transfer may occur by generating a mask or reticle having a desired pattern therein, transferring the pattern to a photoresist, and then patterning the layer using the photoresist as a mask. Other techniques may use direct writing of photoresist, for example using an electron beam. Many other layer-forming techniques also may be used.
It is known that the results of a fabrication process may be impacted by the specific design patterns that are being transferred to a layer. For example, a local pattern density of a physical design can impact the shapes and/or dimensions of the features that are being patterned in the layer. In particular, when an area occupied by a desired pattern on an integrated circuit substrate is small, more etch time may be needed compared to when the area is occupied by a pattern that is large. This phenomena is referred to as a “loading effect”. When more etch time is used, the photoresist may be overetched while patterning the layer, and the line width of the layer to be patterned may become smaller than the desired line width. The loading effect may reduce the manufacturing yield of the integrated circuit and/or produce other undesired results. The loading effect is described, for example, in U.S. Pat. No. 5,278,105 to Eden et al., the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
In an attempt to reduce the loading effect, it is known to provide dummy features in a layer of an integrated circuit. Thus, for example, the above-cited U.S. Pat. No. 5,278,105 to Eden et al. describes a design and method for fabricating devices with reduced loading effect. The disclosed design creates dummy features to increase the percentage of material remaining after etch of an active layer. This improves device reliability by preventing resist punch through during etch. Also, yields are improved as no devices are sacrificed to increase the percentage material remaining. Since dummy features are placed on all devices fabricated in a single production process, the percentage material remaining after etch is the same for all devices for a given layer. This allows the same recipe to be used for all devices fabricated by the process, thereby increasing throughput. See the Eden et al. abstract.
It is also known to provide variable density of dummy features, also referred to as “fill shapes” or “dummy patterns”, in order to accommodate a wide range of pattern density variations. For example, U.S. Pat. No. 5,923,563 to Lavin et al. describes a method for adding fill shapes to a chip in a manner which accommodates a wide range of within-chip pattern density variations and provides a tight pattern density control (i) within a chip and (ii) from chip to chip. A grid is imposed over a chip design pattern, wherein each section of the grid contains a portion of the chip design. A pattern density is then determined for each section of the grid, based on that portion of the chip design pattern which lies within the particular grid section. The results of the pattern density determination are used to determine where to place fill shapes in the chip design in order to increase a density value in each section of the grid to that of a target density value. A best fit approximation is provided to the desired pattern density consistent with a set of layout rules for the level being patterned. See the Lavin et al. abstract. Lavin et al. also discloses a technique to provide variable density fill shape generation by calculating a pattern density for the fill pattern, which is then used as an index into a lookup table, to select one of three fill patterns—dense, medium or low—to fill the grid section. See Lavin et al. Column 5, lines 9-48. The disclosure of the Lavin et al. patent is hereby incorporated herein by reference in its entirety as if set forth fully herein.
SUMMARY OF THE INVENTION
Embodiments of the present invention generate dummy patterns for a region of an integrated circuit that is divided into a plurality of buckets by obtaining a local pattern density for a respective bucket and adjusting a density of the dummy pattern for the respective bucket as a continuously variable function of the respective local pattern density and a target density for the region. By providing a continuously variable dummy pattern density, the desired density of the dummy pattern group may be adjusted precisely, to thereby reduce or eliminate loading effects.
According to some embodiments of the invention, the density of the dummy pattern for the respective bucket is adjusted according to a formula in which the density of the dummy pattern is continuously variable. According to other embodiments, the dummy patterns includes a plurality of features of fixed pitch and a size of the features of fixed pitch is increased or decreased as a continuously variable function of the respective local pattern density and the target density for the region. In other embodiments, the features of fixed pitch comprise quadrangles of fixed pitch, and the length of at least one side of the quadrangles of fixed pitch is increased or decreased as a continuously variable function of the respective load pattern density and the target density for the region. In still other embodiments, the features of fixed pitch comprise rectangles of fixed pitch, and the length of at least one side of the rectangles of fixed pitch is adjusted as a continuously variable function of a square root of a difference between the respective local pattern density and the target density for the region, multiplied by an area of the dummy pattern in the respective bucket, divided by a number of dummy patterns in the respective bucket.
According to other embodiments of the present invention, the local pattern density is obtained for a respective bucket, by reading integrated circuit design layout data for the region of the integrated circuit from an integrated circuit design layout database. The integrated circuit design layout data for the region of the integrated circuit is divided into the plurality of buckets. The local pattern density is calculated for a respective one of the buckets. Finally, the dummy region is determined for a respective one of the buckets.
According to yet other embodiments of the invention, after adjusting the density of the dummy pattern for the respective bucket, the dummy pattern for the respective bucket is merged with the integrated circuit design layout data for the respective bucket. Then, the dummy pattern and the integrated circuit design layout data for the buckets is converted into mask data for patterning the region of the integrated circuit.
According to still other embodiments of the invention, the dummy region for the respective bucket is determined by adding at least one
Park Sang-ho
Shin Jae-pil
Yoo Kwang-jai
Yoo Moon-hyun
Dimyan Magid Y
Samsung Electronics Co,. Ltd.
Smith Matthew
LandOfFree
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