Continuously powered mainstore for large memory subsystems

Electrical computers and digital processing systems: support – Computer power control – Power conservation

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G06F 126

Patent

active

061287466

ABSTRACT:
A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.

REFERENCES:
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patent: 5490118 (1996-02-01), Nishioka et al.
patent: 5600841 (1997-02-01), Culbert
patent: 5604709 (1997-02-01), Price
patent: 5675808 (1997-10-01), Gullick et al.
patent: 5898880 (1999-04-01), Ryu

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