Continuous barrier for interconnect structure formed in...

Details Continuous barrier for interconnect structure formed in... Continuous barrier for interconnect structure formed in...

2002-05-31

2004-12-14

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S643000, C438S648000, C438S653000, C438S656000, C438S685000, C438S687000

Reexamination Certificate

active

06831003

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of interconnect structures within integrated circuits, and more particularly, to minimizing electromigration failure of an interconnect structure formed in porous low-K dielectric material.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to
FIG. 1
, a cross sectional view is shown of a copper interconnect
102
within a trench
104
formed in an insulating layer
106
. The copper interconnect
102
within the insulating layer
106
is formed on a dense dielectric material
109
deposited on a semiconductor wafer
108
such as a silicon substrate as part of an integrated circuit. The dense dielectric material
109
may be a hardmask layer, an etch stop layer, or a capping layer comprised of SiO
2
(silicon dioxide) or SiN (silicon nitride) for example. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect
102
is typically formed by etching the trench
104
as an opening within the insulating layer
106
, and the trench
104
is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to
FIG. 1
, the insulating layer
106
may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO
2
) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer
106
, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material
110
is deposited to surround the copper interconnect
102
within the insulating layer
106
on the sidewalls and the bottom wall of the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material
110
is disposed between the copper interconnect
102
and the insulating layer
106
for preventing diffusion of copper from the copper interconnect
102
to the insulating layer
106
to preserve the integrity of the insulating layer
106
.
Further referring to
FIG. 1
, an encapsulating layer
112
is deposited as a passivation layer to encapsulate the copper interconnect
102
, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer
112
is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect
102
does not easily diffuse into such a dielectric of the encapsulating layer
112
.
As the density of integrated circuit structures continually increases, the distance between the interconnect structures decreases. As the distance between the interconnect structures decreases, a dielectric material with a low dielectric constant (i.e., a low-K dielectric material) is desired for the insulating layer
106
. The insulating layer
106
being comprised of the dielectric material with a low dielectric constant results in lower capacitance between the interconnect structures. Such lower capacitance results in higher speed performance of the integrated circuit and also in lower power dissipation. In addition, such lower capacitance results in lower cross-talk between the interconnect structures. Lower cross-talk between interconnect structures is especially advantageous when the interconnect structures are disposed closer together as device density continually increases.
Referring to
FIG. 2
, one example of a dielectric material with a low dielectric constant for the insulating layer
106
is a porous dielectric material having pores throughout as known to one of ordinary skill in the art of integrated circuit fabrication. An interconnect opening
116
is formed within the porous dielectric material of the insulating layer
106
for forming an interconnect structure within the interconnect opening
116
. With the porous dielectric material for the insulating layer, the interconnect opening
106
has opened pores
118
at the sidewalls of the interconnect opening
116
.
Referring to
FIG. 3
, in the prior art, as device dimensions continually decrease, a diffusion barrier material
120
that is as thin as possible is deposited on the sidewalls and the bottom wall of the interconnect opening
116
. The diffusion barrier material
120
of
FIG. 3
is similar to the diffusion barrier material
110
of FIG.
1
. Because diffusion barrier materials generally have higher resistance than copper, the diffusion barrier material
120
in the prior art is deposited as thin as possible to minimize resistance of the interconnect structure formed within the interconnect opening
116
.
However, the pores
114
of the insulating layer
106
range in size with the pores
114
having a mean diameter in a range of from about 10 Å (angstroms) to about 200 Å (angstroms), depending on the type of low-K dielectric material of the insulating layer
106
. For example, for OSG (organic spin-on glass), the diameter of the pores are in a range of from about 10 Å (angstroms) to about 40 Å (angstroms) with the mean diameter being about 25 Å (angstroms). On the other hand, for hydrocarbon polymer material, the diameter of the pores are in a higher range being as high as 200 Å (angstroms).
When the thickness of the diffusion barrier material
120
is thinner than a radius of the pores
118
that are opened at the sidewalls of the interconnect opening
116
, the diffusion barrier material
120
that is deposited in a conformal deposition process of the prior art does not completely fill such opened pores
118
at the sidewalls of the interconnect opening
116
. Further referring to
FIG. 3
, when the diffusion barrier material
120
does not completely fill such opened pores
118
at the sidewalls of the interconnect opening
116
, a seed layer of copper
122
that is deposited onto the diffusion barrier material
120
does not reach into the opened pores
118
at the sidewalls of the interconnect opening
116
.
Referring to
FIG. 4
, when a copper conductive fill
124
is grown from the copper seed layer
122
for filling the interconnect opening
116
, voids
126
are formed from the open

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