Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-10-16
2007-10-16
Lam, David (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S201000, C365S233100, C327S202000, C714S726000
Reexamination Certificate
active
11055830
ABSTRACT:
A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functional mode, input data bypasses the master latch and transports directly to the CBL output via the slave latch. The CBL effectively removes the master latch from the circuit in the high speed functional mode. However, in the lower speed test mode, input test data travels via both the master and slave latches to the CBL output.
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Khan Masood Ahmed
Lee Michael Ju Hyeok
Seewann Ed
International Business Machines - Corporation
Kahler Mark P.
Lam David
McBurney Mark E.
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