Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-22
2003-03-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S318000, C257S319000
Reexamination Certificate
active
06534817
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memorys, and more particularly, to a contactless channel write/erase flash memory cell/array and method of fabricating the same.
2. Description of the Prior Art
FIG. 1
is a cross-sectional view illustrating a conventional flash memory cell
10
.
FIG. 2
is a cross-section view illustrating a metal contact structure associated with the conventional flash memory cell structure. Referring to
FIG. 1
, the flash memory cell
10
is built upon a P-substrate
11
including a N-well
12
formed on the P-substrate
11
and a stacked gate
14
formed on the N-well
12
. An N
+
-doped region
16
and an N
+
-doped region
18
, functioning as a source and a drain of the flash memory cell
10
, respectively, are formed two sides of the stacked gate
14
in the N-well
12
respectively. A P-doped region
20
is formed surrounding the N
+
-doped region
18
in the N-well
12
and a P-doped region
22
is formed beneath the stacked gate
14
.
The stacked gate
14
includes a control gate
24
and a floating gate
26
. A word line voltage V
WL
is applied to the control gate
24
for controlling the flash memory cell
10
. The floating gate
26
is in a “floating” state without any direct connection with external circuits for storing charges. A source voltage V
SL
is applied to the N
+
-doped region
16
(source terminal), and a drain voltage V
BL
is applied to the N
+
-doped region
18
(drain terminal).
With these applied voltages, electrons (e
−
) eject from the floating gate
26
to the N
+
-doped region
18
due to the edge Fowler-Nordheim effect and the flash memory cell
10
is programmed. However, upon applying a voltage on the drain terminal, an undesirable depletion region outside the N
+
-doped region
18
is also produced. Furthermore, hot holes (e
+
) will be generated leading to hot hole injection in the presence of lateral electric field. These hot holes can severely affect the normal operation of a flash memory cell
10
. With a short-circuiting connection between the N
+
-doped region
18
of the drain terminal and the P-doped region
20
, the above-mentioned problems can be prevented. Referring to
FIG. 2
, a metal contact
30
penetrates through an N
+
-doped region
32
of each drain terminal and into a P-doped region
34
. A bit line voltage V
BL
is applied to the N
+
-doped region
32
of each drain terminal through the metal contact
30
so that the N
+
-doped region
32
and the P-doped region
34
are short-circuited together.
In addition, a predetermined distance
38
between the metal contact
30
and the stacked gate
36
has to be maintained in the conventional flash memory cell for preventing interferences caused by each other. However, increasing cell density is constantly in demand in current market, and such conventional flash memory cell design apparently can not satisfy such demand.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a contactless channel write/erase flash memory cell by varying a connecting mode of a metal contact to increase memory packing density without affecting the source of a neighboring flash memory cell.
It is another object of the present invention to provide a method of fabricating a contactless channel write/erase flash memory cell.
According to the claimed invention, a flash memory array includes a plurality of contactless channel write/erase flash memory cells, and each memory cell includes a multi-level substrate, a first ion doped region, a floating gate, a tunnel oxide layer, a second ion doped region, a third ion doped region, a fourth ion doped region, two isolating oxide layers, a dielectric layer and a control gate. The tunnel oxide is located on the substrate, and the floating gate is located on the tunnel oxide layer, the first ion doped region acting as a drain is located on one side of the floating gate of the substrate, the second ion doped region is located surrounding a bottom of the first ion doped region, the third ion doped region is located beneath the floating gate with one side bordering on the second ion doped region, the fourth ion doped region that acts as a source is located in the substrate with one side bordering on the third ion doped region, the two isolating oxide layers are located on the first ion doped region and the fourth ion doped region respectively, the dielectric layer is located on the floating gate and the two isolating oxide layers, and the control gate is located above the floating gate and the two isolating oxide layers.
According to the present invention, the control gate of the flash memory cell extends laterally in a word line direction, and the first ion doped region and the second ion doped region extend in a bit line direction. Therefore, a metal contact which a bit line voltage applied to can be designed away from any of the first ion doped region and the second ion doped region of the memory cells in a bit line direction to decrease the number of the metal contact and also to reduce the area of the memory array.
The substrate, from bottom to top, includes a N-substrate, a deep P-well and a N-well. The first ion doped region and the fourth ion doped region are N
+
-doped region formed by implanting phosphorous (P) or arsenic (As) ions, the second ion doped region and the third ion doped region are P-doped region formed by implanting boron (B) ions, and the second ion doped region has a depth much greater than the third ion doped region.
In addition, the first ion doped region and the second ion doped region are short-circuiting together, such as using a metal contact penetrating through junction between the first ion doped region and the second ion doped region, or using a metal contact crossing the exposed first ion doped region and the exposed second ion doped region.
Furthermore, the present invention further provides a fabricating method of a contactless channel write/erase flash memory cell. The flash memory cell is formed on a substrate. First, a shallow P-doped region is formed within the substrate, and then a tunnel oxide layer and a floating gate are formed on the shallow P-doped region, respectively. Next, a deep P-doped region is formed one side of the floating gate in the substrate, and two N
+
-doped regions are formed on the deep P-doped region and another side of the floating gate within the substrate respectively. Two isolating oxide layers are formed on the two N
+
-doped regions, and a dielectric layer is formed on the floating gate and the two N
+
-doped regions. Finally, a control gate is formed on the dielectric layer.
The substrate includes a N-substrate, a deep P-well region and a N-well region. The N-substrate is formed first, and then the deep P-well region is formed on the N-substrate. Finally, an N-well region is formed on the deep P-well region.
At least one bit line metal contact is formed outside the block of the flash memory array. The metal contact penetrates through the isolating oxide layer and the junction between the N
+
-doped region and the deep P-doped region. In an alternative method, the metal contact crosses the exposed N
+
-doped region and the exposed deep P-doped region which short-circuits these two regions.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5650649 (1997-07-01), Tsukiji
patent: 5863822 (1999-01-01), Kanamori et al.
patent: 6369433 (2002-04-01), Derhacobian et al.
patent: 6243289 (2002-06-01), Gonzalez et al.
patent: 6437396 (2002-08-01), Chou
Hsu Ching-Hsiang
Yang Ching-Sung
e-Memory Technology, Inc.
Fenty Jesse A.
Hsu Winston
Lee Eddie
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