Contact scheme for FINFET structures with multiple FINs

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S368000, C257S401000, C257SE27060

Reexamination Certificate

active

08080838

ABSTRACT:
A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.

REFERENCES:
patent: 2005/0202618 (2005-09-01), Yagishita
patent: 2005/0242395 (2005-11-01), Chen et al.
patent: 2005/0285161 (2005-12-01), Kang et al.
patent: 2005/0285186 (2005-12-01), Fujiwara
patent: 2007/0026629 (2007-02-01), Chen et al.
patent: 2007/0161170 (2007-07-01), Orlowski et al.
Choi, J. A. et al., “Large Scale Integration and Consideration of Triple Gate Transistors.” IEDM, 2004, p. 647.

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