Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Utilizing reflow
Reexamination Certificate
2002-10-28
2004-04-06
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Utilizing reflow
C438S780000, C438S781000, C430S311000, C430S330000
Reexamination Certificate
active
06716767
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is broadly directed towards thermoplastics, thermal and photo-curable materials used for manufacturing microelectronic, optoelectronic, optical, microelectromechanical system (MEMS), and sensor devices using contact planarization technology. The materials produce essentially no residual volatile components upon curing.
2. Description of the Prior Art
Advanced integrated circuit (IC) designs are highly dependent upon increasingly complex device-layering techniques to produce semiconductor devices that are more powerful, have lower profiles, and require less energy to operate. This requires more circuits with much finer structures to be integrated into a chip by constructing multiple layers of interconnects and dielectrics on a semiconductor substrate in an appropriate sequence. To construct an IC, many layers containing ultra-fine structures must be patterned onto a semiconductor surface. Materials must be deposited and removed from the surface to construct such ultra-fine structures. Currently, photolithography is the predominant technique used to pattern these ultra-fine structures.
Photolithography involves depositing a photosensitive material, known as a photoresist, onto a semiconductor substrate surface. An optical transparent object (known as a photomask or reticle) having pre-defined images of the structures to be built on a semiconductor surface is placed above the photoresist-coated substrate. An appropriate wavelength of light is illuminated through the optical object. The light either decomposes or cures the exposed area of the photoresist, depending upon the nature of the photoresist and the process. The semiconductor surface is developed to produce the patterned image on the substrate surface, and the device is ready for subsequent processing.
The conditions required to successfully carry out the photolithography process are well known to those skilled in this art. For example, it is important that the photoresist be applied in a specific, uniform thickness to meet depth-of-focus requirements for the photolithography process. Thickness uniformity is a concern not only during the photolithography process, but also for the deposition of other materials onto a substrate surface during semiconductor device fabrication. For instance, if an interlayer dielectric is applied with a non-uniform thickness, the process to open vias will fail to etch completely to the bottom of the layer in the thicker dielectric areas.
Materials can be applied with good thickness uniformity if the surface to be coated is entirely planar. However, if the surface is not planar (i.e., if it has topographic features) materials often do not coat with a uniform thickness, and this can greatly affect the final yield or performance of the device. A coating deposited on top of a topographic surface tends to contour to the topography of the underlying surface, thus producing a non-planar surface.
The multi-layer structure of an IC is made by fabricating one layer on top of another. The first layer of the structure is built on a planar semiconductor surface. As a result, a topographic surface is introduced onto the semiconductor substrate surface. The second layer is built on top of the topographic surface of the first structural layer. As more layers are built on the substrate, the severity of the surface topography increases. The non-planar surface is no longer suitable for constructing the next structural layer. Therefore, the topographic surface needs to be planarized, or flattened, prior to the construction of the next layer. To planarize the topographic surface, techniques such as plasma etch-back, chemical mechanical polishing (CMP), and contact planarization techniques are typically used.
The plasma etch-back techniques involve the deposition of a thick film to smooth the underlying topographic surface to some extent. A better surface planarity can be achieved with a much thicker film. However, a longer plasma etch time is needed to etch thicker films. The deposited film must have a closely matched plasma etch rate to that of the underlying topographic layer material under specific etch parameters. Subsequently, the thick film is etched in a plasma etcher to the underneath topographic layer to improve the surface planarity.
The CMP technique utilizes a slurry solution to mechanically polish the surface against a pad with the assistance of chemical reactions that occur between the substrate material and the slurry solution. A slurry solution containing abrasive particles and certain chemicals is dispensed onto the pad surface. The topographic substrate surface is pressed against the pad. The substrate is then polished with a circular motion against the pad to remove the topography of the surface. CMP is currently used in IC fabrication. The specific requirements and processing conditions for certain materials that need to be planarized are known to those skilled in the art.
Contact planarization provides an alternative to plasma etch-back and CMP techniques to planarize topographic surfaces. The topographic surface is first deposited with a flowable planarization material. Subsequently, the surface is pressed against an optical flat surface, which allows the material to flow around the topographic structures under certain conditions. The material is then hardened either by photo-irradiation or heat to transfer the planarity of the optical flat surface onto the planarized material surface. The planarized material surface is then released from the optical flat object surface. To facilitate the separation, the optical flat object surface can be treated to lower its surface energy. This can be achieved by depositing a thin film of low surface energy material, such as a fluoropolymer or a fluorinated compound, onto the optical flat object surface. Another approach is to put a low surface energy material with comparable surface planarity, such as a disk or film, between the planarization material and optical flat object surface. Examples of low surface energy materials are materials sold under the name Teflon®, fluorocarbon polymers, or the like. The planarized material surface is then plasma etched to the underlying topographic layer, the planarity of the optical flat surface is transferred to the underneath topographic layer, and the topographic surface is then planarized. One requirement of the planarized material is that it needs to possess a plasma etch ratio of approximately 1 in relation to that of the underlying topographic layer material.
Currently materials used for contact planarization and similar technologies contain volatile organic solvents that can remain in the cured films and cause bubble formation in the film during the hardening process. These bubbles form voids and are permanently trapped in the films upon hardening. If the bubbles are formed at the interface of the planarization material and optical flat surface, a rough surface results. In addition, trapped bubbles will deteriorate the integrity of the films as well as their properties. To prevent bubble formation, additional processes and conditions such as pre-bake or post-bake techniques, an elevated processing temperature, a vacuum processing environment, or combinations of these are needed to remove residual solvent from the films prior to the hardening process. The removal of residual solvent can cause film shrinkage. This shrinkage introduces undesirable topography at the surface because of the variation in planarized material thickness across the substrate surface. The film shrinkage is more severe over the underlying recessed areas where a thicker planarization material is deposited. Therefore, the planarity of the surface is reduced.
As described above, the contact planarization process relies on an optical flat surface to make contact with the material surface to be planarized, and the planarization material is confined and planarized to flow between two surfaces. Both the optical flat surface and the planarizing surface are not permeable to
Daffron Mark
Lamb, III James E.
Shih Wu-Sheng
Brewer Science Inc.
Ghyka Alexander
Hovey & Williams, LLP
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