Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-29
2001-04-17
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S310000, C257S311000, C257S312000, C257S506000, C257S532000, C257S905000, C257S906000, C257S908000
Reexamination Certificate
active
06218697
ABSTRACT:
BACKGROUND OF THE INVENTION
The present application claims priority under 35 U.S.C. §119 to Korean Application No. 80586 filed Dec. 31, 1997, the entire contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention is directed to a semiconductor memory device, and in particular, to a contact in a semiconductor memory device and a method of forming the same, such a contact preferably contributing to realization of packing cells in a chip at a high density.
2. Description of the Related Art
In order to electrically interconnect specific devices in semiconductor memory devices, especially, DRAMs (Dynamic Random Access Memories), metal contacts are formed over a silicon substrate, polysilicon layers for a word line and a bit line, and a plate electrode being the upper electrode of a capacitor, respectively. However, prior to formation of these metal contacts, steps are produced between a cell array region and a peripheral region, for example, a core region. These steps arise due to the difference between their deposition heights resulting from deposition of many material layers. In forming the contacts in a semiconductor memory device having such steps, insulating layers at different heights are etched to different depths. That is, a thin portion of an insulating layer is subjected to overetching and a thick portion thereof to underetching, so that it is highly likely to form an incomplete contact.
In particular, when CF
4
is used as an etching solution, as in related art, to form a contact for a plate electrode, its low etch selectivity gives rise to overetching of the plate electrode underlying an insulating layer, making the plate electrode thin, or leaves the insulating layer between the plate electrode and a metal electrode insufficiently etched, resulting in an electrical short. Thus, the use of CF
4
gives undesirable results.
Under these circumstances, a solution to overcome the above problems included extending a plate electrode across a cell array region to a peripheral region, for example, a core region. A metal contact is then formed over this extended plate electrode. A problem with this solution is that the slope between the cell array region having cells and the core region free of cells impedes even formation of the contact. Also, this solution requires that the cell array region be extended to the core region by an area needed for forming the contact therein, eventually decreasing the integration level of the entire semiconductor memory device.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a contact in a semiconductor memory device and a method of forming the same, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
It is an object of the present invention to provide a contact in a semiconductor memory device and a method of forming the same, which contribute to realization of high integration by reducing the area of a cell array region.
To achieve these and other objects, there is provided a semiconductor memory device having a cell array region divided into an active region and a field region, and a peripheral region. The semiconductor memory device includes an access transistor, a capacitor stacked with a storage electrode connected to the active region for the access transistor, a dielectric layer of a high dielectric constant, and a plate electrode in this order, and a plate electrode contact formed over the active region of the cell array region.
The semiconductor memory device may include an insulating layer formed on the capacitor and a contact hole in the insulating layer, the plate electrode contact being formed through the contact hole. The plate electrode contact may be formed over the storage electrode.
These and other objects of the present invention may also be realized by providing a semiconductor memory device including a first area including a memory cell, a second area free of a memory cell, adjacent to the first area, and a plate electrode contact formed in the first area.
The first area may be a cell array region and the second area is a core region. The semiconductor memory device may include an insulating layer formed on the first area and a contact hole in the insulating layer, the plate electrode contact being formed through the contact hole. The semiconductor memory device may include a storage electrode in the first area and wherein the plate electrode contact is formed over the storage electrode.
According to another aspect of the present invention, there is provided a method of forming a contact for a plate electrode in a semiconductor memory device. In the method for use in a semiconductor memory device having a capacitor stacked with a storage electrode, a dielectric layer of a high dielectric constant, and a plate electrode in this order, and an interlayer insulating layer formed on the plate electrode, a contact hole is formed into the interlayer insulating layer on the active region of a cell array region, the contact hole is filled with an electrode forming material, and the resultant structure is patterned.
The forming a contact hole may include positioning the contact hole over the storage electrode on the active region of the cell array region. The forming a contact hole may include etching the insulating layer using an etching solution having a high etch selectivity between the insulating layer and the plate electrode.
These and other objects of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5312769 (1994-05-01), Matsuo et al.
patent: 5583356 (1996-12-01), Yoon et al.
patent: 5689126 (1997-11-01), Takaishi
patent: 5798903 (1998-08-01), Dhote et al.
patent: 5828096 (1998-10-01), Ohno et al.
Jones Volentine, L.L.C.
Lee Eddie C.
Samsung Electronics Co,. Ltd.
Warren Matthew E.
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