Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-10-04
2003-04-29
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S597000, C438S622000, C438S657000
Reexamination Certificate
active
06555450
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a contact forming method for a semiconductor device, more particularly to a contact forming method by which a direct contact (DC contact) resistance and a buried contact (BC contact) resistance can be lowered by performing ion-implantation only one time.
2. Description of the Related Art
As the high integration rate in a semiconductor device increases, the area of the memory cell accordingly rapidly decreases. The wiring line area in a memory cell and the gap between the wiring lines also have decreased. In addition, the contact area being formed to electrically connect the isolated-device regions has been required to be miniaturized. There has been a concerted effort to concentrate efforts on increasing the capacitance per unit area in a DRAM. The result is a capacitor over bit-line structure (COB) in which a capacitor is formed after the formation of bit-line has been introduced.
In such a COB structure, the bit line is electrically connected to a drain region of a transistor by the DC contact, and a source region of the transistor and a storage node, which are lower electrodes of the capacitor, are electrically connected to each other by a BC contact. Accordingly, the highly integrated semiconductor memory necessarily requires the DC contact and the BC contact.
Since forming contact holes (in which contacts contacting with such source/drain regions are to be formed) cause misalignment, the contact hole forming regions are formed with pad poly-silicon layers to prevent such a misalignment. When the pad poly-silicon layers are applied, the misalignment error of photoresist can be overcome even in a sub-micron application.
However, as the contact size decreases, there is a problem of speed delay caused by high resistances of the DC contact and the BC contact, i.e., RC delay occurs. Particularly, the problem is, contact resistance of the DC contact or BC contact with the pad poly silicon layer increases when contact sizes are less than 0.1 micrometer (&mgr;m).
FIG. 1
shows a conventional semiconductor memory device having DC contact and BC contact structure, e.g., a DRAM device. The (a) area illustrates a cell array region, the (b) area illustrates an active region of an NMOS transistor of the peripheral circuit and the (c) area illustrates a gate node contact region. The DC contact and BC contact forming method in accordance with a conventional prior art will be explained as follows with reference to the accompanying FIG.
1
.
Referring to (a) and (b), the active region
12
and the device isolation region
14
are formed on the silicon substrate
10
. The gate oxide layer
16
is formed on the silicon substrate
10
and the device isolation region
14
. The polycide gates
18
,
20
and the capping oxide layer
22
are formed in series. Thereafter, the spacer oxide layer
30
is formed in a cell array region. The conductive impurities-doped pad poly silicon layer
32
is formed between the spacer oxide layers
30
, and the cell array region is covered by a photoresist.
Next, the spacer oxide
30
a
is formed in an active region of the NMOS transistor of the peripheral circuit shown in
FIG. 1
, and the N+ source/drain regions are formed in the active region. The photoresist is removed and the contact holes
34
are formed in the cell array region, active region of the NMOS transistor and gate node contact region, as shown in FIG.
1
. The bit lines
42
,
44
are formed above the DC contact
34
formed in the cell array region, and the BC contact id formed in the cell array region. Thereafter, the poly silicon layer for the storage node is formed.
In case the contact size is more than 0.15 &mgr;m, there is no problem in such a conventional method. Referring to
FIG. 2
showing the resistance distribution in a prior art semiconductor structure having storage and cell pads shown in
FIG. 3
, however, the broad resistance-distribution and high resistance of the poly silicon layer for the storage node from the pad poly silicon layer cause delays in signal transfer speed as follows. In order to solve such a problem, when the pad silicon layer is formed by deposition of doped polysilicon, it may be suggested a method that the doping dosage of the pad poly silicon layer is raised to 1E+21/cm
2
to thereby lower the resistance. But, this method causes another problem. That is, the increase in the doped concentration of the pad poly silicon layer causes a high level of doping to diffuse into the N− source/drain region. As a result, the doped concentration of the N− source/drain of the active region of the NMOS transistor increases. Accordingly, the intensity of the electric field of the N− source/drain increases, thereby causing refresh in a DRAM.
FIGS. 4 and 5
illustrate another conventional contact forming method, in which a plug ion implantation method is applied to the DC contact region in order to solve the problems of the conventional techniques shown in FIG.
1
.
Referring to FIGS.
4
(
a
), (
b
) and (
c
), with the same method as described previously, the DC contact hole
34
is formed above the pad poly silicon layer
32
formed above the active region, and then the contact plug ion implantation on the whole surface is performed according to the same process as shown in FIG.
1
. The poly silicon layer for bit line, BC contact and storage node, which is formed in such a way shown in FIG.
5
.
By carrying out the contact ion-implantation into the DC contact holes
34
formed in the cell array region, NMOS transistor active region, and field gate node contact region respectively, as shown in FIG.
5
(
a
), (
b
), (
c
), the silicide gate contact in the surrounding region is improved and at the same time the DC contact resistance in the cell array region is improved. However, the additional plug ion implantation causes an additional process requiring additional time and cost. Also, the DC contact resistance in the DC contact region is improved, but the BC contact portion still has the conventional problem.
SUMMARY OF THE INVENTION
Accordingly, in order to solve the aforementioned problems it is an object of the present invention is to provide a method of fabricating a contact of the semiconductor memory device by which the resistances of a DC contact and a BC contact are prevented from being increased, and it is another object of the present invention to provide a method of fabricating a semiconductor memory device in which ion-implantations into a cell array region and an NMOS surrounding region are simultaneously carried out using the N+ source/drain ion-implantation procedure when an active region of the NMOS transistor of the peripheral circuit is formed, thereby preventing increase in the resistances of the DC contact and BC contact.
In accordance with the objects of the present invention, there is provided a contact forming method of a semiconductor memory device including a cell array region and the surrounding circuit region comprises steps of:
forming gates in the cell array region, active region of the surrounding circuit region, and a field insulating layer of the surrounding circuit region and forming source and drain in the active region;
forming an insulating layer on a whole surface on the surrounding circuit region and the cell array region, and forming a spacer by etching the insulating oxide layer in the cell array region, and thereafter forming conductive impurities-doped poly silicon layer on all the resultant regions;
patterning the poly silicon layer formed on the cell array region, and etching the poly silicon layer and the insulating layer formed on the surrounding circuit region, thereafter forming a spacer insulating layer on a side wall of gate of the surrounding circuit region;
thinning the capping insulating layer formed on the gate formed in the cell array region and the surrounding circuit region for ion-implantation of conductive impurities; and
forming a high concentration of doping region on the poly silicon layer formed in
Ban Hyo-Dong
Han Myoung-hee
Jang Won-Hee
Lee Jin-Hun
Min Eun-young
Marger & Johnson & McCollom, P.C.
Quach T. N.
Samsung Electronics Co,. Ltd.
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