Contact capping local interconnect

Details Contact capping local interconnect Contact capping local interconnect

2000-12-20

2004-01-20

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S618000, C257S750000, C257S758000, C257S762000, C257S766000, C257S773000, C257S774000

Reexamination Certificate

active

06680514

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method and structure for forming a metallic capping interface between a damascene conductive wire/stud and a damascene conductive wiring level.
2. Related Art
FIG. 1
depicts a front cross-sectional view of an electronic structure
10
having an insulative layer
14
on a substrate layer
12
, wherein the insulative layer
14
covers electronic devices that exist within and on the substrate layer
12
, in accordance with the related art.
The electronic devices shown in
FIG. 1
that exist within and on the substrate layer
12
include a FET
20
, a FET
30
, and a FET
40
. The FET
20
includes a source
21
, a drain
22
, a gate
23
, a gate insulator
24
, and insulative spacers
25
, wherein the source
21
and the drain
22
my be interchanged in position. The FET
30
includes a source
31
, a drain
32
, a gate
33
, a gate insulator
34
, and insulative spacers
35
, wherein the source
31
and the drain
32
may be interchanged in position. The FET
40
includes a source
41
, a drain
42
, a gate
43
, a gate insulator
44
, and insulative spacers
45
, wherein the source
41
and the drain
42
may be interchanged in position. As in addition to, or instead of, including the FET
20
, the FET
30
, and the FET
40
, the substrate layer
12
may include other electronic devices such as, inter alia, bipolar transistors, diodes, etc. The electronic devices (e.g., the FET
20
, the FET
30
, and the FET
40
), are insulatively separated from one another by insulative barriers, such as, inter alia, the shallow trench isolations
26
,
36
,
46
, and
47
.
The insulative layer
14
may include, inter alia, a insulative material
49
such as phososilicate glass (PSG) or borophososilicate glass (BPSG) formed by any method known to one of ordinary skill in the art such as by high density plasma chemical vapor deposition (HDPCVD), plasma enhanced CVD, ozone/TEOS CVD, LPCVD, etc. The thickness of the insulative layer
14
is between about 0.2 microns and about 1.5 microns and a representative thickness in the aforementioned thickness range is about 0.5 microns. A passivating layer
48
(e.g., a silicon nitride or a silicon carbide layer) may be formed on the substrate layer
12
prior to forming the insulative layer
14
. The passivating layer
48
may act as an etch stop layer during a subsequent reactive ion etching (RIE) of trenches or vias
51
,
52
,
53
, and
54
as described infra in conjunction with FIG.
2
. The passivating layer
48
may also act as a mobile ion barrier, and/or as a copper diffusion barrier, or a diffusion barrier of any other metal, for protecting the substrate layer
12
and the electronic devices (i.e., the FET's
20
,
30
, and
40
) from subsequent etching of trenches or vias into the insulative material
49
as described infra in conjunction with
FIG. 2
, or from moble ions or metals (e.g., Na, Cu, etc.) diffusing into the electronic devices (i.e., the FET's
20
,
30
, and
40
).
FIG. 2
depicts
FIG. 1
after trenches or vias
51
,
52
,
53
, and
54
have been etched in the insulative layer
14
, exposing a portion of each electronic device (i.e., the FET's
20
,
30
, and
40
). The process for forming the trenches or vias
51
,
52
,
53
, and
54
may be any process known to one of ordinary skill in the art such as, inter alia, reactive ion etch (RIE) using perfluoro carbon-based or related (i.e., CH
X
F
Y
, S
X
F
X
, etc.) selective etching or non-selective etching. The process for forming the trenches or vias
51
,
52
,
53
, and
54
removes portions of both the insulative layer
14
and the passivating layer
48
. The trenches or vias
51
,
52
,
53
, and
54
may be of the same width or of different widths. The trenches or vias
51
,
52
,
53
, and
54
serve as a template for forming conductive wires/studs (i.e., wires are formed in trenches and vias provide a conductive path that connect different wiring levels of a multilevel wiring structure) as will be described infra in conjunction with FIG.
3
A. Unless otherwise stated, “conductive” herein means “electrically conductive.”
FIG. 3A
depicts
FIG. 2
after the trenches or vias
51
,
52
,
53
, and
54
have been filled with conductive material to form conductive wires/studs
61
,
62
,
63
, and
64
, respectively, that conductively contact the electronic devices (i.e., the FET's
20
,
30
, and
40
). The conductive wires or studs
61
,
62
,
63
, and
64
may includes any one or more conductive materials such as a semiconductor material (e.g., polysilicon), a metal (e.g., tungsten, tantalum, aluminum, TiN, copper, etc.), or a metallic alloy. Although any of preceding conductive materials may be used, an optimal conductive material is tungsten, which is typically is deposited over thin refractory conductive liners
65
,
66
,
67
, and
68
, as will be discussed infra. The conductive material may be formed by a method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., that grows the conductive material from the bottom and sidewalls of the trenches or vias
51
,
52
,
53
, and
54
. The conductive wires/studs
61
,
62
,
63
, and
64
which include the conductive material are damascene wires/studs and collectively constitute a damascene wiring level. The conductive material so grown merges together from the bottom and sidewalls of the trenches or vias
51
,
52
,
53
, and
54
to typically form internal seams or voids
71
,
72
,
73
, and
74
, respectively. The seams or voids
71
,
72
,
73
, and
74
are oriented lengthwise (i.e., approximately in a direction
99
) within the conductive wires/studs
61
,
62
,
63
, and
64
, respectively. The seams or voids
71
,
72
,
73
, and
74
may extend from above bottom surfaces of the conductive wires/studs
61
,
62
,
63
, and
64
(e.g., from above a bottom surface
55
of the conductive wire/stud
62
) to top surfaces of the conductive wires/studs
61
,
62
,
63
, and
64
, respectively (e.g., to a top surface
56
of the conductive wire/stud
62
). The seams or voids
71
,
72
,
73
, and
74
are problematic as will be discussed infra in conjunction with FIG.
3
B and FIG.
3
D. The seams or voids
71
,
72
,
73
, and
74
in the wire/studs
61
,
62
,
63
, and
64
, respectively, can be magnified or exacerbated by the chemical mechanical polish, etchback, and/or post planarization cleans used for damascening the metal in the trenches. The post planarization cleans can include either wet chemical etching or reactive ion etching.
Additionally, conductive liners
65
,
66
,
67
, and
68
may be formed on the bottom and sidewalls of the trenches or vias
51
,
52
,
53
, and
54
, respectively, as shown. The conductive liners
65
,
66
,
67
, and
68
include one or more conductive materials such as refractory metals and nitrides thereof (e.g., such as titanium, titanium nitride, etc). The conductive wire/stud
61
is conductively coupled to the gate
23
of the FET
20
. The conductive wire/stud
62
is conductively coupled to the drain
22
of the FET
20
. The conductive wire/stud
63
is conductively coupled to the gate
33
of the FET
30
. The conductive wire/stud
64
is conductively coupled to the gate
43
and drain
42
of the FET
40
. The conductive wires/studs
61
,
62
,
63
, and
64
could alternatively be conductively coupled to source rather than drain of the FET's
20
,
30
, and
40
if the positions of the sources
21
,
31
, and
41
were respectively interchanged with the drains
22
,
32
, and
42
of the FET's
20
,
30
, and
40
, respectively.
The filling of the trenches or vias
51
,
52
,
53
, and
54
with the conductive material may be followed with polishing, such as by chemical mechanical polishing (CMP), or any other suitable method (e.g., etchback using a SF
6
based plasma), that planarizes the top surface
17
of the insulative layer
14
and the conductive wires/studs or interconnects
61
,
62
,
63
, and
64
, and removes excess meta

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