Construction of PBGA substrate for flip chip packing

Details Construction of PBGA substrate for flip chip packing Construction of PBGA substrate for flip chip packing

1997-08-18

1999-09-28

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257701, 257697, 257698, 257778, H01L 25053, H01L 2312, H01L 2314

Patent

active

059593482

ABSTRACT:
The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

REFERENCES:
patent: 3617817 (1971-11-01), Kawakatsu
patent: 4710798 (1987-12-01), Marcantonio
patent: 5710071 (1998-01-01), Beddingfield et al.
patent: 5798563 (1998-08-01), Feilchenfeld et al.
Tsukada, Tsuchida, Mashimoto, "Surface Laminar Circuit Packaging," Yasu Technology Application Laboratory, IBM Japan, IEEE, 1992, pp. 22-27.
Wu, Tsukada, Chen, "Materials and Mechanics Issues in Flip-Chip Organic Packaging," 1996 Electronic Components and Technology Conference, IEEE, pp. 524-534.
Powell, Trivedi, "Flip-Chip on FR-4 Integrated Circuit Packaging, "1993 Electronic Components and Technology Conference, IEEE, pp. 182-186.

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