Connector arrangement for a semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257306, 257308, 257368, 257401, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

055833560

ABSTRACT:
In a semiconductor memory device having a novel structure of a wiring layer and a large capacitance capacitor and the manufacturing method therefor, on the transistor formed on the semiconductor substrate, a first conductive layer is formed extending along with the gate electrode of the transistor and connecting with the gate electrode, a storage electrode of a capacitor is formed on the first conductive layer by interposing the insulation film between the first conductive layer and the source region of the transistor, and a second conductive layer is formed in connection with the first conductive layer at a portion between memory cell array and the peripheral circuit region. Storage electrodes can be made thicker without affecting to the step-difference between memory cells and the peripheral circuit region, so that a more reliable semiconductor memory device with a capacitor having a larger capacitance can be realized.

REFERENCES:
patent: 5386382 (1995-01-01), Ahn
Kimura et al., "A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-line Structure," (IEDM 1988) pp. 596-599.

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