Conformal thin films over textured capacitor electrodes

Details Conformal thin films over textured capacitor electrodes Conformal thin films over textured capacitor electrodes

1999-12-03

2004-08-24

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S761000, C438S765000, C438S780000, C438S790000

Reexamination Certificate

active

06780704

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to forming thin films over textured bottom electrodes, and more particularly to providing high permittivity dielectric and top electrode materials with near perfect conformality over memory cell bottom electrodes including hemispherical grain (HSG) silicon.
BACKGROUND OF THE INVENTION
When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned, layer by layer, to build up the desired circuit. Many types of circuits incorporate capacitors, each of which include a dielectric layer sandwiched two plates or electrodes. Memory chips such as dynamic random access memories (DRAMs), in particular, employ capacitors to store charge in memory cells. Each memory cell can represent one bit of data, where the capacitor can either be charged or discharged to represent logical states.
In accordance with the general trend in the semiconductor industry, integrated circuits are continually being scaled down in pursuit of faster processing speeds and lower power consumption. As the packing density of memory chips continues to increase, each capacitor in the more crowded memory cell must still maintain a certain minimum charge storage to ensure reliable operation of the memory cell without excessive refresh cycling. It is thus important that, with progressive generations of circuit design, capacitor designs achieve ever higher stored charge for the shrinking area of the chip (or footprint) allotted to each cell. Techniques have therefore been developed to increase the total charge capacity of the cell capacitor for a given footprint allotment.
The amount of charge stored on the capacitor is proportional to the capacitance, C=kk
0
A/d, where k is the permittivity or dielectric constant of the capacitor dielectric between two electrodes; k
0
is the vacuum permittivity; A is the electrode surface area; and d is the spacing between the electrodes, also representing the thickness of the inter-electrode dielectric. Early techniques have focused on increasing the effective surface area of the electrodes by creating folding structures for stacked capacitors or trench capacitors. Trench capacitors are formed within the semiconductor substrate in which the transistors are generally formed, whereas stacked capacitors are formed above the transistors. Such structures better utilize the available chip area by creating three-dimensional shapes to which the conductive electrodes and capacitor dielectric conform.
FIG. 1A
illustrates a memory cell
10
incorporating an exemplary stacked capacitor above a semiconductor substrate
12
. The illustrated capacitor design is known in the industry as a “stud” capacitor. Transistors are first formed, including gate stacks
14
formed over the substrate
12
and heavily doped active areas
16
within the substrate
12
. A contact
18
reaches through an, insulating layer
20
that overlies the transistors. This contact
18
electrically connects a lower or storage electrode
22
, of the capacitor
11
, which is formed over the insulating layer
20
. The stud shape presents a larger surface area for the lower electrode
22
, relative to the footprint of the substrate over which it is formed. A thin capacitor dielectric layer
24
coats the lower or bottom electrode
22
, and an upper or top electrode
26
is formed over the capacitor dielectric
24
.
FIG. 1B
, for example, illustrates a memory cell
10
a
with a different stacked capacitor design, where like parts are referred to by like reference numerals. As in
FIG. 1B
, a capacitor
11
a
is shown over a substrate
12
, including transistors covered with an insulating layer
20
. The capacitor
11
a
, however, conforms to a generally cylindrical shape. In particular, a lower or bottom electrode
22
a
, electrically connecting to an underlying transistor by the contact
18
, conforms to a cylinder, presenting a larger surface area relative to the footprint of the substrate over which it is formed. With both inner and outer surfaces exposed, as shown, the bottom electrode
22
a
has an even larger effective surface area than the corresponding bottom electrode
22
of the stud capacitor
11
in
FIG. 1A. A
thin capacitor dielectric layer
24
a
coats the bottom electrode
22
a
, and a top electrode
26
a
is formed over the capacitor dielectric
24
a
. “Crown” structures are similar to the illustrated cylindrical capacitor
11
a
of
FIG. 1B
but further include multiple concentric cylinders. Other stacked capacitor designs resemble mushroom shapes, finned structures, pins and a variety of other complicated structures formed above a semiconductor substrate.
FIG. 2
, in contrast to the stacked capacitors of
FIGS. 1A and 1B
, illustrates a memory cell
30
incorporating an exemplary trench capacitor
31
, formed largely within a semiconductor substrate
32
. As with the stacked capacitors of the previous figures, a transistor includes a gate stack
34
over the substrate
32
and heavily doped active areas
36
within the substrate
32
. The drain region (one of the active areas
36
) electrically contacts a lower or storage electrode
42
of the capacitor
31
. Doping or otherwise making conductive the walls of a trench in the semiconductor substrate
32
forms this lower electrode
42
. By conforming to the walls of the trench, a larger surface area is provided for the lower electrode
42
, relative to the footprint of the substrate
32
in which it is formed. A thin capacitor dielectric layer
44
coats the bottom electrode
42
, and a top or reference electrode
46
is formed over the capacitor dielectric
44
.
Relying solely on such structures for increasing the capacitance of the memory cell, however, becomes impractical with advancing generations of memory chip circuit designs. The surface area of a stud capacitor can theoretically be increased infinitely simply by increasing the height of the bottom electrode. Similarly, the depth of trench capacitors can be increased almost to the thickness of the substrate within which it is formed. Unfortunately, limits are imposed upon the height or depth of features in integrated circuits. As is well known in the art, it can be difficult to conformally coat, line or fill features with high steps using conventional deposition techniques. Additionally, increased topography on a chip can adversely affect the resolution of later photolithographic processes.
Rather than relying solely upon the height or depth of the cell capacitor, therefore, a microstructure can be added to further increase the surface area of the capacitor electrodes, by providing a textured or roughened surface to the macrostructural folds of the lower electrode. For example, polycrystalline conductive materials can be roughened by preferentially etching along grain boundaries, as disclosed, for example, in U.S. Pat. No. 3,405,801, issued to Han et al. Alternatively, U.S. Pat. No. 5,372,962, issued to Hirota et al., describes various selective etch processes for perforating a polysilicon layer.
Another class of electrode texturing techniques involves formation of hemispherical grained (HSG) silicon. Several methods for forming HSG silicon are known, including direct deposition, whereby deposited polysilicon selectively grows over nucleation sites, and redistribution anneal of amorphous silicon, whereby thermal energy causes silicon atoms to migrate about a surface and conglomerate about nucleation sites.
FIGS. 1A and 1B
show the lower electrodes
22
,
22
a
including HSG silicon microstructures
28
,
28
a
formed over the basic stud or cylinder configurations, thereby increasing the effective electrode surface area. Similarly, the bottom electrode
42
of
FIG. 2
includes an HSG silicon layer
48
over the basic trench configuration, further increasing the electrode surface area.
In order to fully realize the advantage of the increased surface area of textured bottom electrodes, the capacitor dielectric layer should conform closely to the surface of the bottom electrode. Whil

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