Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
2000-09-22
2004-05-04
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C326S041000
Reexamination Certificate
active
06732263
ABSTRACT:
A related application is filed concurrently with the present application as U.S. patent application Ser. No. 09/668,665 in the names of May et al. and entitled “Bus Architecture for System on a Chip” and assigned to the present assignee. Another related application is filed concurrently with the present application as U.S. patent application Ser. No. 09/668,202 in the names of May et al. and entitled “A Fully Re-Configurable Memory Map” and assigned to the present assignee.
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits. More specifically, the present invention is directed at configuring a PLD having embedded logic.
A programmable logic device (PLD) is an integrated circuit, which can be customized by a system designer to perform different logical functions. PLDs combine the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. By using these devices, custom logic functions can be designed and fabricated in-house, while eliminating long engineering lead times, high tooling costs, and dedicated inventory problems associated with custom devices. Furthermore, the design can be easily changed without upsetting design schedules and purchase agreements.
PLDs often comprise a plurality of generic logic blocks that may be arbitrarily programmed and interconnected to each other. These blocks may be implemented using volatile memory such as static random access memory (SRAM) or, alternatively, with nonvolatile memory such as erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), fuses, and antifuses. If the programmable elements are volatile memories, the memory cells must be configured upon system power-up in order for the device to operate as desired. This is typically done by loading configuration data from an external configuration source into the PLD. The configuration source may be, for example, a nonvolatile memory such as a FLASH memory. Configuration of the PLD is accomplished by transferring the configuration data from the configuration source to the PLD.
Recently, there has been a trend to embed other logic devices such as within a PLD. Embedded devices (i.e. “embedded logic”) may comprise control logic and other application specific logic devices such as, volatile memory, non-volatile memory, cache, etc. and are embedded prior to configuration of the programmable logic core. A processor (or central processing unit CPU)) may also comprise part of the embedded logic. A processor is an integrated circuit implemented on a semiconductor chip, which typically includes, among other things, an instruction execution unit, register file, arithmetic logic unit (ALU), multiplier, etc. Processors are found in digital systems, such as personal computers for executing instructions, and can also be employed to control the operation of most digital devices.
While the addition of embedded logic has proven to be desirable, there remains a it need of a method for setting up (i.e., configuring) embedded logic devices, in addition to configuring the PLD core.
SUMMARY OF THE INVENTION
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.
In a first aspect of the present invention, a method of configuring a system having a programmable logic device and embedded logic is disclosed. The method includes the step of supplying a single serialized configuration bit stream to the system. The bit stream is characterized by a unique protocol and includes a first configuration data section for configuring the programmable logic device and a second configuration data section for configuring the embedded logic.
In a second aspect of the invention a digital system having a programmable logic device and embedded logic coupled to the programmable logic device is disclosed. A configuration source is provided to supply a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.
In a third aspect of the invention, a configuration apparatus for providing configuration data to a system on a chip is disclosed, the system including embedded logic and a programmable logic device. The configuration apparatus comprises a configuration data bit stream register having a header including an address field containing an address of a logic device within the embedded logic, and a data field containing data configuration data for configuring the logic device.
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Draper Andrew
May Roger
Altera Corporation
Chang Eric
Lee Thomas
Townsend and Townsend / and Crew LLP
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