Amplifiers – Modulator-demodulator-type amplifier
Reexamination Certificate
2002-11-19
2004-05-11
Nguyen, Patricia (Department: 2817)
Amplifiers
Modulator-demodulator-type amplifier
C330S251000
Reexamination Certificate
active
06734725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to power amplifiers and, more specifically, to a power amplifier for producing an output signal by conversion of an input signal into a pulse modulation signal and by power amplification.
2. Description of the Related Art
Class D amplifiers are known as power amplifiers for audio. Class D amplifiers amplify power by switching, each of which has a circuit configuration, for example, shown in FIG.
6
.
In this circuit, an input digital audio signal Pin (hereinafter, referred to as “input signal Pin”) is supplied through an input terminal Tin to pulse width modulation (PWM) circuits
11
and
12
. The input signal Pin is converted into a pair of PWM signals PA and PB.
The pulse duration of the PWM signals PA and PB varies in accordance with the level of the input signal Pin (the instantaneous level of the signal obtained by digital to analog conversion of the input signal Pin). However, as shown in
FIG. 8
, one PWM signal PA has a pulse duration corresponding to the level of the input signal Pin, and the other PWM signal PB has a pulse duration corresponding to the 2's complement of the level of the input signal Pin. The rise time of the PWM signals PA and PB is set to the start of one cycle time Tc of the PWM signals PA and PB, and the fall time of them varies in accordance with the level of the input signal Pin. In other words, the pulse duration of the PWM signal PA and that of the PWM signal PB always add up to one cycle time Tc in every period.
The carrier frequency fc (=1/Tc) of the PWM signals PA and PB is, for example, 16 times as large as the sampling frequency fs of the input signal Pin. The carrier frequency fc is calculated by the following equation, when fs is 48 kHz:
fc=
16
fs=
16×48
kHz=
768
kHz
One PWM signal PA is supplied to a drive circuit
13
to produce a pair of drive voltages +PA and −PA, which are shown in part A of FIG.
7
. The drive voltage +PA has the same level as the signal PA, whereas the drive voltage −PA has the inverted level thereof. The drive voltages +PA and −PA are fed to the respective gates of a pair of switching elements, for example, N channel MOS FETs (metal oxide semiconductor field-effect transistors) Q
11
and Q
12
.
In this case, the FETs Q
11
and Q
12
constitute a push-pull circuit
15
, in which the drain of the FET Q
11
is connected to a power terminal TPWR, while the source thereof is connected to the drain of the FET Q
12
. The source of the FET Q
12
is grounded. A stable DC voltage +VDD of, for example, 20V to 50V is supplied as a power supply voltage to the power terminal TPWR.
Both the source of the FET Q
11
and the drain of the FET Q
12
are connected to one end of a speaker
19
through a low-pass filter
17
including a coil and a capacitor.
The other PWM signal PB is fed to the speaker
19
in the same manner as the PWM signal PA. Namely, the PWM signal PB is supplied to a drive circuit
14
to produce a pair of drive voltages +PB and −PB, which are shown in part B of FIG.
7
. The drive voltage +PB has the same level as the signal PB, whereas the drive voltage −PB has the inverted level thereof. The drive voltages +PB and −PB are fed to the respective gates of a pair of N channel MOS FETs Q
13
and Q
14
constituting a push-pull circuit
16
.
Both the source of the FET Q
13
and the drain of the FET Q
14
are connected to the other end of the speaker
19
through a low-pass filter
18
including a coil and a capacitor.
Referring to part C of
FIG. 7
, when +PA=“H” and −PA=“L”, the FET Q
11
switches ON, whereas the FET Q
12
switches OFF. Thus, the voltage VA at the node between the FET Q
11
and Q
12
equals +VDD. In contrast, when +PA=“L” and −PA=“H”, the FET Q
11
switches OFF, whereas the FET Q
12
switches ON, and therefore VA is equal to zero.
Similarly, referring to part D of
FIG. 7
, when +PB=“H” and −PB=“L”, the FET Q
13
switches ON, whereas the FET Q
14
switches OFF. Thus, the voltage VB at the node between the FET Q
13
and Q
14
equals +VDD. In contrast, when +PB=“L” and −PB=“H”, the FET Q
13
switches OFF, whereas the FET Q
14
switches ON, and therefore VB is equal to zero.
At VA=+VDD and VB=0, a current i flows from the node between the FETs Q
11
and Q
12
to the node between the FETs Q
13
and Q
14
through a line including the low-pass filter
17
, the speaker
19
, and the low-pass filter
18
in series, as shown in FIG.
6
and part E of FIG.
7
.
At VA=0 and VB=+VDD, a reverse current i flows from the node between the FETs Q
13
and Q
14
to the node between the FETs Q
11
and Q
12
through a line including the low-pass filter
18
, the speaker
19
, and the low-pass filter
17
in series. In contrast, at VA=VB=+VDD and at VA=VB=0, no current i flows. That is, the push-pull circuits
15
and
16
constitute a BTL (Bridged-Tied Load) circuit.
The period during which the current i flows varies in accordance with the period during which the original PWM signals PA and PB rise. Also, the current i is integrated by the low-pass filters
17
and
18
when the current i flows through the speaker
19
. As a result, the current i flowing through the speaker
19
is a power-amplified analog current corresponding to the level of the input signal Pin. That is, a power-amplified output is supplied to the speaker
19
.
The circuit shown in
FIG. 6
serves as a power amplifier. In this circuit, the FETs Q
11
to Q
14
amplify power by switching the power supply voltage +VDD in accordance with the input signal Pin, thereby achieving high efficiency and high power output.
Generally, the rise time and the fall time of pulse voltage cannot be completely zero. Also in the power amplifier described above, the rising edges and the falling edges of the drive voltages +PA and −PA are slightly inclined, for example, as shown in parts A and B of FIG.
9
. In this situation, the FETs Q
11
and Q
12
turn on simultaneously, even transiently, during the rising edges and the falling edges of the drive voltages +PA and −PA, so that a short-through current flows through the FETs Q
11
and Q
12
.
Similarly, the FETs Q
13
and Q
14
turn on simultaneously, even transiently, during the rising edges and the falling edges of the drive voltages +PB and −PB, so that a short-through current flows through the FETs Q
13
and Q
14
.
In a method for suppressing such a short-through current, as shown in parts B and C of
FIG. 9
, a time delay is caused between the edges of the drive voltage +PA and those of the drive voltage −PA attributable to the slight delay of the drive voltage +PA. In this case, the FETs Q
11
and Q
12
never turn on simultaneously, thereby suppressing a short-through current flowing through the FETs Q
11
and Q
12
. A short-through current does not flow through the FETs Q
13
and Q
14
, either.
However, with this method, the period during which output voltages VA and VB are +VDD is delayed, thus shortening the period during which the current i flows. As a result, the signal current supplied to the speaker
19
suffers distortion.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power amplifier for suppressing a short-through current without varying the output current i.
A power amplifier of the present invention includes a first pulse modulation circuit for converting an input signal into a first pulse modulation signal indicating the level of the input signal and for outputting the first pulse modulation signal; a second pulse modulation circuit for converting the input signal into a second pulse modulation signal indicating the 2's complement of the level of the input signal and for outputting the second pulse modulation signal; a first
Masuda Toshihiko
Ohkuri Kazunobu
Nguyen Patricia
Sony Corporation
Wolf Greenfield & Sacks P.C.
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