Configuration memory structure

Details Configuration memory structure Configuration memory structure

2007-03-27

2007-03-27

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S203000, C365S230030, C326S038000, C326S040000, C326S041000

Reexamination Certificate

active

11254558

ABSTRACT:
A configuration memory structure includes one or more distributed buffers cascaded together, the output of a first buffer driving an output data line and complementary output data line which terminate at the input of a succeeding buffer. The first buffer includes precharging elements connected between a source and the data line and complementary data line, respectively; data sensing and holding elements connected between respective input and complementary input data lines and the data line and complementary data line, respectively; and tristate elements connected to the outputs of the data sensing and holding elements. This scheme provides fast and reliable configuration and configuration read back, especially for a high density FPGA.

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