Configuration and method for the low-loss writing of an MRAM

Details Configuration and method for the low-loss writing of an MRAM Configuration and method for the low-loss writing of an MRAM

2001-08-03

2003-10-28

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S008000, C365S055000, C365S066000, C365S171000

Reexamination Certificate

active

06639829

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a configuration for the low-loss writing of an Magneto-Resistive Random Access Memory (MRAM) having a plurality of cells that are provided between respective word lines and bit lines in a cell field, whereby, given writing into a particular memory cell, a voltage drop occurs on the selected word line and bit line that are connected to such a cell.
FIG. 4A
is a schematic illustration of a conventional MRAM cell with a word line WL running in direction y and a bit line BL running in the perpendicular direction x, which crosses the word line at a distance. Between the word line WL and the bit line BL, there is a conventional memory cell Z, shown in
FIG. 4B
, which includes a hard-magnetic layer
1
, a tunnel barrier layer
2
, and a soft-magnetic layer
3
disposed in a layer stack between the word line WL and the bit line BL.
To store the desired data item in such an MRAM cell, a current I
WL
is impressed on the word line WL, and a current I
BL
is impressed on the bit line BL. These currents I
WL
and I
BL
generate magnetic fields B
WL
and B
BL
, respectively. Thus, at the crossing of the word line WL and bit line BL, i.e., in the region of the memory cell Z, a magnetic field B
xWL
runs in direction x due to the current I
WL
flowing through the bit line BL, and a magnetic field B
yBL
runs in direction y due to the current I
BL
flowing through the bit line BL. The total magnetic field B formed by the sum of the two magnetic fields B
xWL
and B
yBL
directs the soft-magnetic layer
3
of the cell Z in a particular direction, which may be parallel or antiparallel to the magnetization of the hard-magnetic layer
1
. The memory cell Z thus stores a logical 1 or 0 depending upon the parallel or antiparallel magnetization of the two layers
1
and
3
, to which a low or high resistance value is allocated, respectively.
In a write operation, the word line current I
WL
flows through the word line WL. But because the word line WL has a resistance R
L
in each of its subsections between individual bit lines BL
0
, BL, . . . , a voltage drop U
L
occurs in each subsection as a result of the line resistance along the word line WL. Such voltage drop U
L
brings about voltage differences U
Z0
, U
Z1
, U
Z2
, . . . across the individual cells Z, thereby causing parasitic currents I
par0
, I
par1
, I
par2
, . . . to flow through the cells Z, as represented in FIG.
5
.
The current I
WL
flowing in the word line WL is damped along the word line WL by these parasitic currents I
par0
, I
par1
, . . . , and, therefore, reliable writing, which requires a certain intensity of the current I
WL
in the word line WL, can no longer be guaranteed. In other words, due to the parasitic currents I
par0
, I
par1
, . . , the strength of the current I
WL
flowing in the word line WL must be elevated.
But such an elevation of the current I
WL
flowing in the word line WL is limited, because an excessive current I
WL
in the word line WL could lead to the writing of all cells along such a word line WL without the co-operation of a respective bit line BL
0
, BL
1
. In other words, given an excessively high current in the word line WL, it is no longer possible to select the memory cells.
To keep the parasitic currents I
par0
, I
par1
, . . . optimally small given these conditions, it would be imaginable either to provide for an optimally high resistance of the memory cells or to shorten the length of the word lines WL. However, both measures are associated with material disadvantages in that high resistances of the memory cells reduce the read current through these cells and, thus, complicate a reliable reading. On the other hand, short word lines reduce the efficiency of the MRAM, that is to say, of the memory chip, and, thus, raise the cost of production. The same concerns arise with respect to the bit lines, accordingly.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a configuration for the low-loss writing of an MRAM that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides a configuration for the low-loss writing of an MRAM that utilizes neither high cell resistances nor short word lines and/or bit lines.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a configuration for low-loss writing of a magneto-resistive random access memory, including a cell field having word lines, bit lines, and memory cells disposed in the cell field between respective ones of the word lines and the bit lines. The memory cells are configured to have a voltage drop occur on a selected one of the word lines connected to a particular one of the memory cells when writing into the particular one of the memory cells and to have voltages at the bit lines set to minimize a cell voltage across the memory cells between a selected one of the word lines and individual ones of the bit lines.
In the configuration according to the invention, the voltages at the bit lines and word lines are set such that the cell voltage across the memory cells between the selected word line and the individual bit lines, and between the selected bit line and individual word lines, is minimal.
In the configuration, the cell voltage that arises in the write operation and the parasitic currents flowing through the individual cells are reduced or even eliminated by suitably adjusting or regulating the voltages at the individual bit lines and word lines.
With the objects of the invention in view, there is also provided a configuration for the low-loss writing of a magneto-resistive random access memory, including a cell field having word lines, bit lines, and memory cells disposed in the cell field between respective ones of the word lines and the bit lines. The memory cells are configured to have a voltage drop occur on a selected one of the word lines connected to a particular one of the memory cells when writing into the particular one of the memory cells, the selected word line having two ends, and when a voltage V
1
and a voltage V
2
<V
1
are present at a respective one of the two ends of the selected word line, the cell field is configured to have all of the bit lines set to voltages (V
1
+V
2
)/2 and to have a maximum cell voltage of ±(V
1
−V
2
)/2.
To accomplish the result, there are principally two variants, which will be described in detail below with reference to a selected word line. The relations that are described for the selected word line also substantially apply to a selected bit line. A combination of a selected word line and a selected bit line is also possible: whereas all bit lines are controlled to a voltage of the selected word line, at the same time all word lines are controlled to the voltage of the selected bit line.
(a) When the voltage drop along a word line has the magnitude V
1
−V
2
, with V
1
being the voltage at one end of the word line and V
2
being the voltage at the other end, then all bit lines are set to the voltage (V
1
−V
2
)/2. A maximum cell voltage of ±(V
1
−V
2
)/2 is then present. Accordingly, the parasitic currents that flow in across the memory cells on one half of the word line flow out again on the other half of the word line. In other words, in the variant, the bit lines are all set to a separate equipotential precisely midway between U
1
and U
2
.
(b) In a second variant, in contrast to variant (a), the voltages of the individual bit lines are not set to an equipotential. Rather, they are individually conditioned to the voltage drop along the word line so that the voltage across the individual memory cells is approximately zero, and practically no parasitic current will flow. Because the measuring of the word line voltage at each individual cell along the selected word line to recover reference voltages demands a large chip area, a reference word line is expediently inserted, which simulates the selected word line and from

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