Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Patent
1993-10-03
1995-01-24
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
257692, H01L 2348, H01L 2946, H01L 2962, H01L 2964
Patent
active
053844882
ABSTRACT:
A semiconductor chip (12) includes a plurality of bond pads (16). A plurality of bond shelves (28) are located along opposed end edges (20, 22) of the chip (12). The bond pads (16) are oriented in selected areas remote from the bond shelves (28). A via (42) is formed through an insulating layer (38) to the surface of the bond pad (18) to provide electrical connection thereto. A metallization layer (44) is formed over the an insulating layer (38), filling the via (42). The metallization layer (44) is patterned and etched to form a patten of trace lines (18) spatially separated to connect each bond pad (16) to bond shelves (28).
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Golshan Shahin
Rhodine Craig W.
St. Martin Craig A.
Brady, II Wade James
Clark S. V.
Donaldson Richard L.
Holland Robby T.
James Andrew J.
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