Configurable plasma volume etch chamber

Details Configurable plasma volume etch chamber Configurable plasma volume etch chamber

2001-06-29

2003-03-04

Dang, Thi (Department: 1763)

Adhesive bonding and miscellaneous chemical manufacture

Differential fluid etching apparatus

Having glow discharge electrode gas energizing means

C156S345470, C118S7230ER

Reexamination Certificate

active

06527911

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to plasma etching chambers with controlled plasma volume using a plurality of confinement structures.
2. Description of the Related Art
In semiconductor fabrication, plasma etching is commonly used to etch conductive and dielectric materials. Plasma etch chambers are typically used which are capable of etching selected layers deposited over a substrate as defined by a photoresist mask. In general, the processing chambers are configured to receive processing gases, and radio frequency (RF) power is applied to one or more electrodes in the processing chamber. The pressure within the chamber is controlled in accordance with a particular desired process. Upon applying the desired RF power to the electrode(s), the process gases in the chamber are activated such that a plasma is created. The plasma is configured to perform the desired etching of the selected layers of a semiconductor wafer.
In order to perform the desired etching of the selected layers of a semiconductor wafer, the plasma is typically configured by manipulating variations in such parameters as pressure, electron density, flow rate, and the like. In order to achieve the desired plasma parameter variations within a single processing environment, examples of modifiable parameters include the chemistry of the gases, the pressure within the chamber, and the amount of RF power applied to the RF electrode(s) within the chamber. The prior art, however, does not provide for the variation of the volume of plasma within a single chamber. Without the ability to vary the volume of plasma in a single processing chamber, it is generally necessary to utilize a plurality of differently-configured processing chambers in order to achieve optimum plasma characteristics for particular etching applications. The plurality of processing chambers need to be compatible within a processing system of etch chambers, or capable of being positioned and operated in close proximity to other processing chambers to ensure economical and efficient wafer transfer between process chambers for the various stages of etch processing.
Dual damascene fabrication includes a common multi-step etching process which illustrates a range of processing environments required for optimum feature fabrication.
FIG. 1A
is a flow chart diagram
100
illustrating the method operations for the etching processes of a typical via-first dual damascene fabrication process. The flow chart diagram
100
begins after the substrate has been deposited with the various layers that will define fabricated features, and the first photolithography process has been performed to define the first etching operation. The first etch process is performed in operation
102
in which a via structure is etched. In a typical via etching operation, at least two dielectric layers are etched to form the via structure.
FIG. 1B
shows an exemplary substrate
120
, over which has been deposited a barrier layer
126
a
, first dielectric layer
122
, an optional etch stop layer
126
b
, and a second dielectric layer
124
. A photoresist layer
128
a
has been patterned to enable the etching of a via
130
through the second dielectric layer
124
, the etch stop layer
126
b
, and the first dielectric layer
122
. In one example, the material properties of the first dielectric layer
122
and the second dielectric layer
124
are different and require that two separate etching operations using two distinct etch chemistries be performed to fabricate the via
130
structure. Returning to
FIG. 1A
, the first etch process
102
includes one or more etching operations required to completely define the via structure
130
.
The method continues with operation
104
in which the remaining photoresist layer
128
a
(
FIG. 1B
) is removed. As is known, photolithography is used to define features in semiconductor manufacturing. In the instant example, the locations of the vias were first defined and then the via structures were etched. The remaining photoresist is removed in operation
104
so that the next feature can be defined and etched.
The method continues with operation
106
in which the next feature in the fabrication operation is patterned. By way of example, a next layer of photoresist is coated and then imaged to define the next feature, the trench structures. Using photolithography, the trenches are next defined in accordance with known feature fabrication processes.
The method advances to operation
108
in which the second etch process is performed. The second etch process in the instant example is the etching of the trench structures.
FIG. 1C
shows the exemplary structure of
FIG. 1B
in which a via
130
was etched as described in operation
102
above. The photoresist
128
b
has been removed to define the trench structure
132
which is etched through the second dielectric layer
124
and to the etch stop layer
126
b.
Returning once again to
FIG. 1A
, the method advances to operation
110
in which the remaining photoresist
128
b
(
Figure 1C
) is removed. Once the second etch process is completed and the trench structures are fabricated, the remaining photoresist used to define the trench structures is removed.
The method continues with operation
112
in which the silicon nitride (SiN) layers are etched, and the method is done.
FIG. 1D
shows the completed features defined using etching processes in the example fabrication of a dual damascene structure. The barrier layer
126
a
that was within the via feature
130
is etched to expose the substrate
120
. The etch stop
126
b
that was in the trench feature
132
between the first dielectric layer
122
and the second dielectric layer
124
is likewise etched. Both the etch stop
126
b
, an optional layer depending on the particular structure and process, and the barrier
126
a
are typically layers of SiN, the removal of which are the final etching steps in the instant dual damascene fabrication example. As is known, the etching processes are typically followed by deposition of barriers and/or metallization to fabricate the trenches and vias of the dual damascene structure.
As illustrated in the flow chart diagram
100
of
FIG. 1A
, at least three separate etching, and two photoresist removal, operations are performed in the etching processes of a typical dual damascene fabrication operation. As will be described in greater detail below, the first etch process is best suited for a large volume plasma etch environment. Typically, in a large volume environment, high ion energy, also known as high bias voltage, is achieved at the surface of the substrate. In a large volume environment, high plasma flow rate is achieved at a low pressure. Because the first etch process includes etching through two dielectric layers in addition to an optional SiN etch stop layer, the higher bias at a higher flow rate are the desired plasma characteristics. A high plasma volume containment environment provides the optimal conditions for the most effective and efficient plasma.
The removal of photoresist is most optimally performed in a small volume oxygen plasma environment. In a small volume environment, the plasma is maintained very close to the surface of the wafer. The plasma achieved is generally very high density, and yields a very high photoresist removal rate. Additionally, in a small volume environment, ion energy to the wafer is low so that sputtering of the dielectric material can be minimized. A small plasma volume containment environment is generally desired for photoresist removal.
The second etch process can be either a large plasma volume environment or a small plasma volume environment, and needs to be optimized in accordance with the materials utilized. By way of example, the etch stop layer
126
b
(
FIGS. 1B
,
1
C, and
1
D) is an optional layer. Further, the first dielectric layer
122
and the second dielectric layer
124
can be of various similar or disparate dielectric materials, and

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