Configurable memory design for masked programmable logic

Details Configurable memory design for masked programmable logic Configurable memory design for masked programmable logic

1999-04-28

2002-12-10

Decady, Albert (Department: 2133)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C714S733000

Reexamination Certificate

active

06492833

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits, and more particularly to architectures for programmable logic integrated circuits.
Programmable logic integrated circuits are well known to those in the electronic art. Such programmable logic integrated circuits are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), CPLDs (Complex Programmable Logic Devices) EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for specific applications. Such devices include, for example, the well-known Classic™, MAX®, and FLEX® families of EPLDs manufactured by Altera Corp.
The popular FLEX® PLD architecture from Altera Corp. includes many logic array blocks (LABs) arranged in a two-dimensional array and multiple embedded array blocks (EABs). This PLD architecture further includes two arrays of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs, the EABs, and the device I/O pins. Each LAB includes a number of programmable logic elements (LEs) that provide relatively elementary logic functions such as NAND, NOR, exclusive OR, flip flops, and other functions. The LABs are generally used to implement general logic and the EABs are generally used to implement memory and specialized logic functions.
A user configures a programmable logic integrated circuit, such as a PLD or a FPGA, to implement the desired logical functions. For example, the user may configure a PLD to be a microcontroller, a microprocessor, a multiplier, a digital filter, or the like. During the design phase, due to circumstances such as errors in the design or changes in requirements, the user may need to modify the design by reconfiguring the PLD. Once a particular design for the PLD has been successfully implemented and tested, the design typically does not need to be changed again. At that point, it may be desirable to reduce production costs by implementing the design in a lower cost device such as a mask-programmable PLD (MPLD).
A MPLD is a device that is configured or “hard-wired” during the fabrication of the device. For example, the PLD manufacturer fabricates a MPLD design by using a specific metal mask corresponding to the user's design. Conventionally, the conversion from a programmable design into a MPLD design is time consuming and inefficient. These design hurdles are contrary to the low cost and fast time to market requirements of many electronics products.
As can be seen, techniques for efficient conversion of a design from a programmable design to a MPLD design is highly desirable. Further, it is important that the MPLD provides the available functionality of the programmable design it replaces.
SUMMARY OF THE INVENTION
The invention provides techniques that expedite the design conversion from a PLD to a MPLD. For a MPLD conversion in accordance with the invention, the logic and interconnects of the PLD design are synthesized using conventional design conversion techniques. The embedded memories of the PLD are substituted with configurable memory blocks that provide the embedded memory features. The configurable memory block can be designed and stored in a design library, to be recalled and included in the MPLD design when needed. The contents of a ROM in the configurable memory block are altered from one MPLD design to the next.
A specific embodiment of the invention provides a mask programmable integrated circuit that includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear (i.e., preload of zeros) of the RAM or a preload of contents of the ROM to the RAM. The clear or preload can be performed after achieving a successful self-test of the RAM. In an embodiment, the RAM has a variable word length and depth size and can be configured to operate in one of many modes. In an embodiment, the integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the ROM and the RAM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM. With the preload feature, the invention can emulate a ROM, a preloaded RAM, or look-up table logic functions as well as conventional RAM. Further, the BIST allows for testing of the RAM without the need for external support.
Another specific embodiment of the invention provides a method of initializing a mask programmable integrated circuit. The method includes: (1) resetting the mask programmable integrated circuit; (2) providing a signal to indicate a reset condition has occurred; (3) initiating a self-test of the RAMs of the mask programmable integrated circuit; and (4) when the self-test has successfully completed, preloading the RAM with contents from a ROM. The self-test of the integrated circuit typically includes performing a test of the RAM. In one embodiment, the RAM test can be performed by: (1) writing a sequence of predetermined values to the RAM; (2) reading a sequence of values from the RAM; and (3) comparing the sequence of values read from the RAM against the sequence of values written to the RAM. Alternatively, the RAM test can be achieved by performing a cyclic redundancy check (CRC) of values received from the RAM. The RAM test can also be performed using conventional RAM test algorithms.
The invention can be used to replace embedded memories (e.g., RAMs) of any PLD and integrated circuits, including microprocessors, digital signal processors, controllers, and others.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.


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