Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Patent
1997-09-19
2000-03-28
An, Meng-Ai T.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
710 52, 710 53, 710 54, 711149, 711100, 711170, 714 5, 714 7, G06F 1314
Patent
active
060444169
ABSTRACT:
A first-in first-out (FIFO) memory interface is provided by coupling an input register and an output register to a conventional static random access memory (SRAM). The registers and SRAM are coupled to control logic that controls the timing of shift-in (write) and shift-out (read) operations. Upon receipt of a write request signal, input data is received from the requesting device and buffered within the input register. The buffered data is then stored in the SRAM during a write operation. Upon receipt of a read request signal, the data previously buffered in the output register is provided to the requesting device and during an associated read operation the next stored data in the SRAM is retrieved and buffered within the output register. The control logic is programmable and is therefore capable of supporting different SRAM configurations. The control logic can also be implemented in a conventional programmable logic device.
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Quality Semiconductor, Inc. "High Speed CMOS 4K .times.9 FIFO with Output Enable", all pages Jun. 6, 1995.
Quality Semiconductor, inc., "High-Speed CMOS 1K .times.36 Clocked FIFO with Bus Sizing", all pages, Jul. 17, 1995.
Andre Dehon, "Transit Note #188 Notes on Coupling Processors with Reconfigurable Logic", pp. 18-19, Mar. 21, 1995.
Tom Jackson, Texas Instruments, "Parity-Generate and Parity-Check Features for High-Bandwidth Computing FIFO Applications", all, Mar. 1996.
Quality Semiconductor Inc., "High-Speed CMOS 256 .times.36 2 Bi-directional FIFO", all, Apr. 24, 1995.
Aiello Jeffrey P.
An Meng-Ai T.
Samsung Electronics Co,. Ltd.
Sherman, Esq. Kenneth L.
Whitmore Stacy
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