Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2002-01-14
2004-06-08
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S230050, C365S230060, C365S230020
Reexamination Certificate
active
06747903
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits and in particular, to a dual-port memory within a programmable logic integrated circuit.
Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modem programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also include embedded user-programmable memory or RAM.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality and flexibility in programmable logic integrated circuits. For example, the memory ports should be configurable to meet the requirements of the application designed in the programmable logic. Specifically, the memories should have configurable input and output data word widths. This is true particularly in networking and DSP applications. But this flexibility should not come at the expense of circuit complexity, die area, or power dissipation. Also, for greatest flexibility, the memory should be a true dual-port, capable of either reading or writing from both ports at the same time.
What is needed is a highly flexible memory, with independently configurable dual read and write ports.
SUMMARY OF THE INVENTION
An exemplary embodiment of the present invention provides a dual-port SRAM in a programmable logic device. The dual-port SRAM has configurable input and output data word widths. To accomplish this, conforming logic is placed in front of conventional write column and read column address decoders, and multiplexing circuits are inserted in the write and read data paths. The conforming logic and multiplexing circuits are controlled by data bits stored in a configuration RAM. These bits are referred to as CRAM bits.
Another exemplary embodiment of the present invention provides a method of writing to a memory. The method includes receiving an address portion having a first number of address bits. A second number of address bits of the address portion are blocked, where the second number is less than the first number. A third number of address bits are not blocked; the third number plus the second number equal the first number. The third number of address bits are decoded, and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are then written to the selected memory cells.
A further exemplary embodiment of the present invention provides a method of reading from a memory. The method includes receiving an address portion including a first number of bits, blocking a second number of bits of the address portion, the second number less than the first number, and passing a third number of bits of the address portion. The third number summed with the second number is equal to the first number. A fourth number of data bits are read from a fourth number of memory cells, and the third number of bits are decoded in order to multiplex a first number of data bits to a fifth number of outputs.
Another exemplary embodiment of the present invention provides an integrated circuit. The integrated circuit includes an address conforming logic block configured to receive a first number of address bits, block a second number of address bits, and pass a third number of address bits. Also included are an address decoder coupled to the address conforming logic block configured to decode the third number of address bits and provide a fourth number of column select signals, and a memory array having memory cells arranged in rows and columns, configured to receive the fourth number of column select signals.
Yet a further exemplary embodiment of the present invention provides an integrated circuit. This integrated circuit includes an address conforming logic block configured to receive a first number of address bits, block a second number of address bits, and pass a third number of address bits. Also included are an address decoder coupled to the address conforming logic block configured to decode the third number of address bits and provide a fourth number of column select signals, a memory array having memory cells arranged in rows and a fifth number of columns, and a fifth number of sense amplifiers coupled to the memory array, configured to provide a fifth number of read data bits.
A further exemplary embodiment provides an integrated circuit. This integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, address configuration means for receiving a plurality of address bits including a first portion of address bits and a second portion of address bits, blocking the first portion of address bits, and providing the second portion of address bits. Also included are an address decoder means for receiving the second portion of address bits and providing a plurality of select lines. The plurality of select lines selects a plurality of columns of memory cells in the memory array. Also included is a data multiplexer means for receiving a plurality of data bits and the plurality of select lines, and multiplexing the plurality of data bits to the plurality of columns of memory cells in the memory array.
A further exemplary embodiment provides another integrated circuit. This integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, sense amplifier means for reading data from the columns of memory cells in the memory array and providing a plurality of read data bits, and address configuration means for receiving a plurality of address bits comprising a first portion of address bits and a second portion of address bits, blocking the first portion of address bits, and providing the second portion of address bits. Also include are an address decoder means for receiving the second portion of address bits and providing a plurality of select lines, and data multiplexer means for receiving the plurality of read data bits and the plurality of select lines, and multiplexing a first portion of the plurality of read data bits to a plurality of output data lines.
A better understanding of the nature and advantages of the present invention may be gained with reference to the following detailed description and the accompanying drawings.
REFERENCES:
patent: 6020759 (2000-02-01), Heile
patent: 6396302 (2002-05-01), New et al.
patent: 6459303 (2002-10-01), Chang et al.
Chang Tzung-Chin
Chong Yan
Huang Joseph
Kim In Whan
Nguyen Khai
Altera Corporation
Le Vu A.
Townsend and Townsend / and Crew LLP
Zigmant J. Matthew
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